> The first ARM was microcoded RISC != (ARM only) Second, it is totally normal, when production get non-ideal product, but lot of compromises. Whole idea of

> The first ARM was microcoded RISC != (ARM only) Second, it is totally normal, when production get non-ideal product, but lot of compromises. Whole idea of CISC, it have relatively simple hardware, but many thing made under the hood by software (microcode), because of this for CISC is normal commands lasts more than 20 cycles (in PDP was commands with 48 cycles), while others could be 3-8 cycles. RISC avoid long operations. Even more, whole idea of RISC to made hardware extremely straightforward and unified, so ideally ALL commands work with same count of cycles. But remember about compromises. Power of CISC was that it's microcode could been updated much easier than RISC hardware, because of this even for some IBM, sure CISC processors exists option, to create for EACH client unique CPU with its own opcodes. Sorry, even more - for some IBM processors was possible to load new microcode on boot time, and they even build on this their line of mainframes, in which in top machines nearly all standard opcodes was hardware supported, but in cheapest machines, most things calculated by microcode. For RISC, yes, exists also for ARM option, to include client opcodes, but this was totally different time and totally different price.