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For me exists pure CISC, RISC, etc, and some hybrid cases. Most real life cases are hybrid, unfortunately. Pure CISC very easy to define - it have microcode,

by simne 3y ago

For me exists pure CISC, RISC, etc, and some hybrid cases. Most real life cases are hybrid, unfortunately. Pure CISC very easy to define - it have microcode, because of this could exist complex commands with few operands. Pure RISC does not have microcode, it is fully pipeline. So for me, 6502 is CISC with RISC-like tricks.

kjs3 3y ago
The first ARM was microcoded.[1] The DEC Alpha used microcode (nee PALcode) for a number of functions. There are RISC-V implementations using microcode.[2] Not all CICS chips use microcode. Indeed, you can make an argument the 6502 and Z80 don't have microcode rather a ROM sequencer. Depends on how fine you want to grind your axe. [1] https://www.righto.com/2016/02/reverse-engineering-arm1-processors.html https://www.righto.com/2016/02/reverse-engineering-arm1-proc... [2] https://github.com/gsmecher/minimax https://github.com/gsmecher/minimax
- simne 3y ago
  > The first ARM was microcoded RISC != (ARM only) Second, it is totally normal, when production get non-ideal product, but lot of compromises. Whole idea of CISC, it have relatively simple hardware, but many thing made under the hood by software (microcode), because of this for CISC is normal commands lasts more than 20 cycles (in PDP was commands with 48 cycles), while others could be 3-8 cycles. RISC avoid long operations. Even more, whole idea of RISC to made hardware extremely straightforward and unified, so ideally ALL commands work with same count of cycles. But remember about compromises. Power of CISC was that it's microcode could been updated much easier than RISC hardware, because of this even for some IBM, sure CISC processors exists option, to create for EACH client unique CPU with its own opcodes. Sorry, even more - for some IBM processors was possible to load new microcode on boot time, and they even build on this their line of mainframes, in which in top machines nearly all standard opcodes was hardware supported, but in cheapest machines, most things calculated by microcode. For RISC, yes, exists also for ARM option, to include client opcodes, but this was totally different time and totally different price.
  - kjs3 3y ago
    From your post: Pure CISC very easy to define - it have microcode, because of this could exist complex commands with few operands. Pure RISC does not have microcode, it is fully pipeline. You are wrong, I gave examples where you are wrong, and now you're trying to change the narrative so you appear to be right. Have a little integrity.
    - simne 3y ago
      You have rights to have your own view. Unfortunately, your words does not convince me. Now thank you. Have a nice day!

by simne 3y ago

kjs3 3y ago

The first ARM was microcoded.[1] The DEC Alpha used microcode (nee PALcode) for a number of functions. There are RISC-V implementations using microcode.[2] Not all CICS chips use microcode. Indeed, you can make an argument the 6502 and Z80 don't have microcode rather a ROM sequencer. Depends on how fine you want to grind your axe. [1] https://www.righto.com/2016/02/reverse-engineering-arm1-processors.html https://www.righto.com/2016/02/reverse-engineering-arm1-proc... [2] https://github.com/gsmecher/minimax https://github.com/gsmecher/minimax

simne 3y ago
> The first ARM was microcoded RISC != (ARM only) Second, it is totally normal, when production get non-ideal product, but lot of compromises. Whole idea of CISC, it have relatively simple hardware, but many thing made under the hood by software (microcode), because of this for CISC is normal commands lasts more than 20 cycles (in PDP was commands with 48 cycles), while others could be 3-8 cycles. RISC avoid long operations. Even more, whole idea of RISC to made hardware extremely straightforward and unified, so ideally ALL commands work with same count of cycles. But remember about compromises. Power of CISC was that it's microcode could been updated much easier than RISC hardware, because of this even for some IBM, sure CISC processors exists option, to create for EACH client unique CPU with its own opcodes. Sorry, even more - for some IBM processors was possible to load new microcode on boot time, and they even build on this their line of mainframes, in which in top machines nearly all standard opcodes was hardware supported, but in cheapest machines, most things calculated by microcode. For RISC, yes, exists also for ARM option, to include client opcodes, but this was totally different time and totally different price.
- kjs3 3y ago
  From your post: Pure CISC very easy to define - it have microcode, because of this could exist complex commands with few operands. Pure RISC does not have microcode, it is fully pipeline. You are wrong, I gave examples where you are wrong, and now you're trying to change the narrative so you appear to be right. Have a little integrity.
  - simne 3y ago
    You have rights to have your own view. Unfortunately, your words does not convince me. Now thank you. Have a nice day!