Cool, I love weird architectures. This one has attributes in common with an exposed pipeline - the sort of thing where one instruction writes to a register, the

Cool, I love weird architectures. This one has attributes in common with an exposed pipeline - the sort of thing where one instruction writes to a register, then the next 10 cycles can read the stale version from that register, and then the 11th will finally see that value. That's cute from a hardware perspective and deeply confusing to program against. It looks like a register in "straight" is a circular buffer which ticks on instruction execution and a register in "clockhands" is a circular buffer which ticks on writes to the register, which would indeed be a substantial improvement. This is another variant of statically schedule lots of code ahead of time, moving work from the hardware into the compiler. Works really well if basic blocks contain many instructions and memory latency is known in advance, at least to within tight bounds, and you put enough effort into the compiler. Traditionally basic blocks are short and memory latency is all over the place, at which point you really want to schedule things at runtime. Hence CPUs and GPUs - both do a load of nominally avoidable work at program runtime. DSP chips and derivatives can sometimes fix memory latency, at which point this sort of static scheduling can be useful, though there's still the ratio of branch to arithmetic to deal with. As an aside, I'm not convinced by their motivating claim that current processors are power-inefficient. x64 / aarch64 / amdgpu seem to get a lot of maths done per watt.