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From a tech-nerd point of view, here is the reason why I am so excited about RISC-V. RISC-V means there is a possibility of creating a completely open source im

by afr0ck 3y ago

From a tech-nerd point of view, here is the reason why I am so excited about RISC-V. RISC-V means there is a possibility of creating a completely open source implementation of an industry-grade microprocessor, just like the Linux kernel did for operating systems, democratising the business of building advanced microprocessors. I can't work for Intel or Arm design teams. Hardware is not my main job and entry barrier to those companies is so high (without mentioning age and geographic barriers). However, I would have loved if there was a real, industrial, free and open implementation of a microprocessor where you collaborate with smart people all over the world to solve interesting problems and implement advanced hardware designs and algorithms.

fwsgonzo 3y ago
I feel the same way. I think RISC-V has changed my opinion on the hardware aspect of things, and now for the first time I want to try to create a simple CPU at home. There is even a simpler RV32E spec, for those (like me) with little hardware experience. Perhaps RV32E is reasonable to start with? https://five-embeddev.com/riscv-isa-manual/latest/rv32e.html https://five-embeddev.com/riscv-isa-manual/latest/rv32e.html
- brucehoult 3y ago
  The only difference between RV32E and RV32I is 16 registers vs 32. That saves a little silicon die space, or some TTL chips if you're building something like in the 1970s, but it doesn't remove any complexity.
  - GeorgeTirebiter 3y ago
    The 10 cent CH32V003 https://www.wch-ic.com/products/CH32V003.html https://www.wch-ic.com/products/CH32V003.html implements RV32E I find it hard to believe that much silicon is saved these days by having 16 registers vs 32; in fact, I wish they would not have made this extension -- the lowest-end RV CPU possible. In other words, if the minimum were 32 regs, as is standard, maybe such a chip would cost 11 cents. On the 3rd hand, compilers handle 16 regs just fine, and also, the kinds of jobs these 10-cent parts do are no doubt well-served by having 16 registers. $ 4.95 for 50 pieces: https://www.aliexpress.us/item/3256804850399956.html https://www.aliexpress.us/item/3256804850399956.html
    - brucehoult 3y ago
      I'm well aware ... I have some CH32V003 chips and dev board. Very cool little chips: https://www.youtube.com/watch?v=1W7Z0BodhWk https://www.youtube.com/watch?v=1W7Z0BodhWk https://www.youtube.com/watch?v=-4d3PgEXhdY https://www.youtube.com/watch?v=-4d3PgEXhdY The main reason for 16 registers is not even the silicon savings, but decreased interrupt response time from having fewer `A` and `T` registers to save and restore. Standard RISC-V has 15 of them, plus `RA`, which is a lot more than the main microcontroller competition. The downside is that normal code can run 20% to 30% more slowly due to an increased number of register spills to the stack. Interrupt response time is more about the ABI than the ISA, so this could be handled with simply a different ABI, but some people want the smaller silicon size as well. Those who want to can compile `-march=rv32i -mabi=ilp32e` to use the RV32E ABI but also have `x16` to `x31` available as callee save registers. It was initially assumed that only RV32E would be defined, but when RV32E was ratified a year ago, RV64E was also because there has been unexpectedly high demand from chip designers for 64 bit RISC-V with 16 registers, for small and simple controllers in Cortex M0 class, but in a chip with 64 bit applications processors, so the controller can access all of RAM. Both 32 bit ARM and 64 bit x86 have been getting by with 16 registers, but Arm put 32 in their 64 bit ISA, and Intel recently extended x86 to 32 registers (and 3-address instructions!) also.
brucehoult 3y ago
Note that the C910 CPU cores used in this chip are in fact open source: https://github.com/T-head-Semi/openc910 https://github.com/T-head-Semi/openc910 (C920 is just C910 plus RVV draft 0.7.1 vector unit which pretty much no software uses anyway, sadly)
- afr0ck 3y ago
  There is the Berkeley BOOM core as well [1], which is more interesting to me. [1] https://github.com/riscv-boom/riscv-boom https://github.com/riscv-boom/riscv-boom

by afr0ck 3y ago

fwsgonzo 3y ago

I feel the same way. I think RISC-V has changed my opinion on the hardware aspect of things, and now for the first time I want to try to create a simple CPU at home. There is even a simpler RV32E spec, for those (like me) with little hardware experience. Perhaps RV32E is reasonable to start with? https://five-embeddev.com/riscv-isa-manual/latest/rv32e.html https://five-embeddev.com/riscv-isa-manual/latest/rv32e.html

brucehoult 3y ago
The only difference between RV32E and RV32I is 16 registers vs 32. That saves a little silicon die space, or some TTL chips if you're building something like in the 1970s, but it doesn't remove any complexity.
- GeorgeTirebiter 3y ago
  The 10 cent CH32V003 https://www.wch-ic.com/products/CH32V003.html https://www.wch-ic.com/products/CH32V003.html implements RV32E I find it hard to believe that much silicon is saved these days by having 16 registers vs 32; in fact, I wish they would not have made this extension -- the lowest-end RV CPU possible. In other words, if the minimum were 32 regs, as is standard, maybe such a chip would cost 11 cents. On the 3rd hand, compilers handle 16 regs just fine, and also, the kinds of jobs these 10-cent parts do are no doubt well-served by having 16 registers. $ 4.95 for 50 pieces: https://www.aliexpress.us/item/3256804850399956.html https://www.aliexpress.us/item/3256804850399956.html
  - brucehoult 3y ago
    I'm well aware ... I have some CH32V003 chips and dev board. Very cool little chips: https://www.youtube.com/watch?v=1W7Z0BodhWk https://www.youtube.com/watch?v=1W7Z0BodhWk https://www.youtube.com/watch?v=-4d3PgEXhdY https://www.youtube.com/watch?v=-4d3PgEXhdY The main reason for 16 registers is not even the silicon savings, but decreased interrupt response time from having fewer `A` and `T` registers to save and restore. Standard RISC-V has 15 of them, plus `RA`, which is a lot more than the main microcontroller competition. The downside is that normal code can run 20% to 30% more slowly due to an increased number of register spills to the stack. Interrupt response time is more about the ABI than the ISA, so this could be handled with simply a different ABI, but some people want the smaller silicon size as well. Those who want to can compile `-march=rv32i -mabi=ilp32e` to use the RV32E ABI but also have `x16` to `x31` available as callee save registers. It was initially assumed that only RV32E would be defined, but when RV32E was ratified a year ago, RV64E was also because there has been unexpectedly high demand from chip designers for 64 bit RISC-V with 16 registers, for small and simple controllers in Cortex M0 class, but in a chip with 64 bit applications processors, so the controller can access all of RAM. Both 32 bit ARM and 64 bit x86 have been getting by with 16 registers, but Arm put 32 in their 64 bit ISA, and Intel recently extended x86 to 32 registers (and 3-address instructions!) also.

brucehoult 3y ago

Note that the C910 CPU cores used in this chip are in fact open source: https://github.com/T-head-Semi/openc910 https://github.com/T-head-Semi/openc910 (C920 is just C910 plus RVV draft 0.7.1 vector unit which pretty much no software uses anyway, sadly)

afr0ck 3y ago
There is the Berkeley BOOM core as well [1], which is more interesting to me. [1] https://github.com/riscv-boom/riscv-boom https://github.com/riscv-boom/riscv-boom