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I don't really get why people are so excited about RISC-V. An open ISA doesn't really offer any additional freedoms to the user. It does not mean we get truly o

I don't really get why people are so excited about RISC-V. An open ISA doesn't really offer any additional freedoms to the user. It does not mean we get truly open hardware. This whole thing is just about Chinese companies not wanting to pay for ARM licenses anymore. Which is good for them but I don't get the excitement from tech people. Even if a RISC-V CPU would someday offer the same performance for the same price than an x86-64 counterpart, it would be a strictly worse deal, as software support will be so much worse. The x86 monoculture was an amazing time to live in and helped us enjoy so much backwards compatibility. The promised lower power-consumption might be nice but we will have to see how much the ISA really matters for that.

2OEH8eoCRo0 3y ago
I don't get why people trust PRC-fabbed silicon. You couldn't pay me to put anything that comes from these fabs on my home network.
afr0ck 3y ago
From a tech-nerd point of view, here is the reason why I am so excited about RISC-V. RISC-V means there is a possibility of creating a completely open source implementation of an industry-grade microprocessor, just like the Linux kernel did for operating systems, democratising the business of building advanced microprocessors. I can't work for Intel or Arm design teams. Hardware is not my main job and entry barrier to those companies is so high (without mentioning age and geographic barriers). However, I would have loved if there was a real, industrial, free and open implementation of a microprocessor where you collaborate with smart people all over the world to solve interesting problems and implement advanced hardware designs and algorithms.
- fwsgonzo 3y ago
  I feel the same way. I think RISC-V has changed my opinion on the hardware aspect of things, and now for the first time I want to try to create a simple CPU at home. There is even a simpler RV32E spec, for those (like me) with little hardware experience. Perhaps RV32E is reasonable to start with? https://five-embeddev.com/riscv-isa-manual/latest/rv32e.html https://five-embeddev.com/riscv-isa-manual/latest/rv32e.html
  - brucehoult 3y ago
    The only difference between RV32E and RV32I is 16 registers vs 32. That saves a little silicon die space, or some TTL chips if you're building something like in the 1970s, but it doesn't remove any complexity.
    - GeorgeTirebiter 3y ago
      The 10 cent CH32V003 https://www.wch-ic.com/products/CH32V003.html https://www.wch-ic.com/products/CH32V003.html implements RV32E I find it hard to believe that much silicon is saved these days by having 16 registers vs 32; in fact, I wish they would not have made this extension -- the lowest-end RV CPU possible. In other words, if the minimum were 32 regs, as is standard, maybe such a chip would cost 11 cents. On the 3rd hand, compilers handle 16 regs just fine, and also, the kinds of jobs these 10-cent parts do are no doubt well-served by having 16 registers. $ 4.95 for 50 pieces: https://www.aliexpress.us/item/3256804850399956.html https://www.aliexpress.us/item/3256804850399956.html
      - brucehoult 3y ago
        I'm well aware ... I have some CH32V003 chips and dev board. Very cool little chips: https://www.youtube.com/watch?v=1W7Z0BodhWk https://www.youtube.com/watch?v=1W7Z0BodhWk https://www.youtube.com/watch?v=-4d3PgEXhdY https://www.youtube.com/watch?v=-4d3PgEXhdY The main reason for 16 registers is not even the silicon savings, but decreased interrupt response time from having fewer `A` and `T` registers to save and restore. Standard RISC-V has 15 of them, plus `RA`, which is a lot more than the main microcontroller competition. The downside is that normal code can run 20% to 30% more slowly due to an increased number of register spills to the stack. Interrupt response time is more about the ABI than the ISA, so this could be handled with simply a different ABI, but some people want the smaller silicon size as well. Those who want to can compile `-march=rv32i -mabi=ilp32e` to use the RV32E ABI but also have `x16` to `x31` available as callee save registers. It was initially assumed that only RV32E would be defined, but when RV32E was ratified a year ago, RV64E was also because there has been unexpectedly high demand from chip designers for 64 bit RISC-V with 16 registers, for small and simple controllers in Cortex M0 class, but in a chip with 64 bit applications processors, so the controller can access all of RAM. Both 32 bit ARM and 64 bit x86 have been getting by with 16 registers, but Arm put 32 in their 64 bit ISA, and Intel recently extended x86 to 32 registers (and 3-address instructions!) also.
- brucehoult 3y ago
  Note that the C910 CPU cores used in this chip are in fact open source: https://github.com/T-head-Semi/openc910 https://github.com/T-head-Semi/openc910 (C920 is just C910 plus RVV draft 0.7.1 vector unit which pretty much no software uses anyway, sadly)
  - afr0ck 3y ago
    There is the Berkeley BOOM core as well [1], which is more interesting to me. [1] https://github.com/riscv-boom/riscv-boom https://github.com/riscv-boom/riscv-boom
dcreater 3y ago
Its so so important for gatekeepers not to exist for free market capitalism to succeed. RISC V is reinstating this state of normalcy..
- wwtrv 3y ago
  As much as free market capitalism can exist when China completely dominates the RISC-V market.
  - brucehoult 3y ago
    Except they don't. At the moment Chinese companies (well, WCH) dominate the stand-alone RISC-V microcontroller market, which has mindshare with engineers designing PCBs well out of proportion to the market size or profitability. Western companies dominate the market for RISC-V cores that are invisibly going into larger chips in huge markets such as mobile phone SoCs made by Apple, Qualcomm, and Samsung. Chinese companies are also at the moment dominating the assembling of RISC-V cores into Linux-capable chips with the large collection of other IP needed for this, and putting those chips on to SBCs. But the CPU cores used are a mix of Chinese and Western ones, with for example SOPHGO's upcoming high performance 16 core SG2380 SoC using American SiFive P670 cores.
whoiscroberts 3y ago
The appeal in my case was thinking with the RISC instruction set, I just picked up the vision v 2 SBC and plan to use it to learn.
sargun 3y ago
Really, I think it’s about competition and monopolies. If enough vendors get behind the ISA, we could see a massive ecosystem flourish, and cheap RISCV chips that are widely available. A bonus would be if enough people are working on the ecosystem, and contributing back, we could get the benefit of all the contributors.
wg0 3y ago
Just speculating and projecting into the future - if world further drifts apart as it currently seems to be the case then both ISAs are US or UK which might come under export control and such. But in theory, that might not happen with an open source ISA though I have not read the fine print on the RISC-V licensing and this euphoria might not be warranted.
kragen 3y ago
the risc-v privileged spec was the first time i looked at a page table structure and thought 'hey, writing a protected-memory operating system doesn't really sound that hard' — though admittedly i haven't done it yet also though rv32i is a pretty nice assembly language, though not quite as nice as arm32. what would be just about perfect would be arm32 with compare-and-branch instructions instead of condition codes, and modeless rv32c-style compressed instructions instead of a whole separate decoder mode that's full of easy ways to confuse your disassembler also, a lot of companies and individuals are doing experimentation with the isa that arm licenses didn't allow them to do there's no arm equivalent to the ch32v003 or serv or even picorv32. picorv32 means you can run linux on an fpga, and it's tantalizingly close to being supported with a fully free toolchain it would be cool if you could write an assembly-language program on a ch32v003 and run it on a supercomputer, but that probably won't be a useful thing to do in practice; rv32 and rv64 are incompatible enough to be problematic, and cramping your code to fit into 16 registers will compromise its performance on your supercomputer, not to mention not using isa extensions like v. and if you don't care about its performance on your supercomputer you might as well just use qemu

2OEH8eoCRo0 3y ago

I don't get why people trust PRC-fabbed silicon. You couldn't pay me to put anything that comes from these fabs on my home network.

afr0ck 3y ago

From a tech-nerd point of view, here is the reason why I am so excited about RISC-V. RISC-V means there is a possibility of creating a completely open source implementation of an industry-grade microprocessor, just like the Linux kernel did for operating systems, democratising the business of building advanced microprocessors. I can't work for Intel or Arm design teams. Hardware is not my main job and entry barrier to those companies is so high (without mentioning age and geographic barriers). However, I would have loved if there was a real, industrial, free and open implementation of a microprocessor where you collaborate with smart people all over the world to solve interesting problems and implement advanced hardware designs and algorithms.

fwsgonzo 3y ago
I feel the same way. I think RISC-V has changed my opinion on the hardware aspect of things, and now for the first time I want to try to create a simple CPU at home. There is even a simpler RV32E spec, for those (like me) with little hardware experience. Perhaps RV32E is reasonable to start with? https://five-embeddev.com/riscv-isa-manual/latest/rv32e.html https://five-embeddev.com/riscv-isa-manual/latest/rv32e.html
- brucehoult 3y ago
  The only difference between RV32E and RV32I is 16 registers vs 32. That saves a little silicon die space, or some TTL chips if you're building something like in the 1970s, but it doesn't remove any complexity.
  - GeorgeTirebiter 3y ago
    The 10 cent CH32V003 https://www.wch-ic.com/products/CH32V003.html https://www.wch-ic.com/products/CH32V003.html implements RV32E I find it hard to believe that much silicon is saved these days by having 16 registers vs 32; in fact, I wish they would not have made this extension -- the lowest-end RV CPU possible. In other words, if the minimum were 32 regs, as is standard, maybe such a chip would cost 11 cents. On the 3rd hand, compilers handle 16 regs just fine, and also, the kinds of jobs these 10-cent parts do are no doubt well-served by having 16 registers. $ 4.95 for 50 pieces: https://www.aliexpress.us/item/3256804850399956.html https://www.aliexpress.us/item/3256804850399956.html
    - brucehoult 3y ago
      I'm well aware ... I have some CH32V003 chips and dev board. Very cool little chips: https://www.youtube.com/watch?v=1W7Z0BodhWk https://www.youtube.com/watch?v=1W7Z0BodhWk https://www.youtube.com/watch?v=-4d3PgEXhdY https://www.youtube.com/watch?v=-4d3PgEXhdY The main reason for 16 registers is not even the silicon savings, but decreased interrupt response time from having fewer `A` and `T` registers to save and restore. Standard RISC-V has 15 of them, plus `RA`, which is a lot more than the main microcontroller competition. The downside is that normal code can run 20% to 30% more slowly due to an increased number of register spills to the stack. Interrupt response time is more about the ABI than the ISA, so this could be handled with simply a different ABI, but some people want the smaller silicon size as well. Those who want to can compile `-march=rv32i -mabi=ilp32e` to use the RV32E ABI but also have `x16` to `x31` available as callee save registers. It was initially assumed that only RV32E would be defined, but when RV32E was ratified a year ago, RV64E was also because there has been unexpectedly high demand from chip designers for 64 bit RISC-V with 16 registers, for small and simple controllers in Cortex M0 class, but in a chip with 64 bit applications processors, so the controller can access all of RAM. Both 32 bit ARM and 64 bit x86 have been getting by with 16 registers, but Arm put 32 in their 64 bit ISA, and Intel recently extended x86 to 32 registers (and 3-address instructions!) also.
brucehoult 3y ago
Note that the C910 CPU cores used in this chip are in fact open source: https://github.com/T-head-Semi/openc910 https://github.com/T-head-Semi/openc910 (C920 is just C910 plus RVV draft 0.7.1 vector unit which pretty much no software uses anyway, sadly)
- afr0ck 3y ago
  There is the Berkeley BOOM core as well [1], which is more interesting to me. [1] https://github.com/riscv-boom/riscv-boom https://github.com/riscv-boom/riscv-boom

dcreater 3y ago

Its so so important for gatekeepers not to exist for free market capitalism to succeed. RISC V is reinstating this state of normalcy..

wwtrv 3y ago
As much as free market capitalism can exist when China completely dominates the RISC-V market.
- brucehoult 3y ago
  Except they don't. At the moment Chinese companies (well, WCH) dominate the stand-alone RISC-V microcontroller market, which has mindshare with engineers designing PCBs well out of proportion to the market size or profitability. Western companies dominate the market for RISC-V cores that are invisibly going into larger chips in huge markets such as mobile phone SoCs made by Apple, Qualcomm, and Samsung. Chinese companies are also at the moment dominating the assembling of RISC-V cores into Linux-capable chips with the large collection of other IP needed for this, and putting those chips on to SBCs. But the CPU cores used are a mix of Chinese and Western ones, with for example SOPHGO's upcoming high performance 16 core SG2380 SoC using American SiFive P670 cores.

whoiscroberts 3y ago

The appeal in my case was thinking with the RISC instruction set, I just picked up the vision v 2 SBC and plan to use it to learn.

sargun 3y ago

Really, I think it’s about competition and monopolies. If enough vendors get behind the ISA, we could see a massive ecosystem flourish, and cheap RISCV chips that are widely available. A bonus would be if enough people are working on the ecosystem, and contributing back, we could get the benefit of all the contributors.

wg0 3y ago

Just speculating and projecting into the future - if world further drifts apart as it currently seems to be the case then both ISAs are US or UK which might come under export control and such. But in theory, that might not happen with an open source ISA though I have not read the fine print on the RISC-V licensing and this euphoria might not be warranted.

kragen 3y ago

the risc-v privileged spec was the first time i looked at a page table structure and thought 'hey, writing a protected-memory operating system doesn't really sound that hard' — though admittedly i haven't done it yet also though rv32i is a pretty nice assembly language, though not quite as nice as arm32. what would be just about perfect would be arm32 with compare-and-branch instructions instead of condition codes, and modeless rv32c-style compressed instructions instead of a whole separate decoder mode that's full of easy ways to confuse your disassembler also, a lot of companies and individuals are doing experimentation with the isa that arm licenses didn't allow them to do there's no arm equivalent to the ch32v003 or serv or even picorv32. picorv32 means you can run linux on an fpga, and it's tantalizingly close to being supported with a fully free toolchain it would be cool if you could write an assembly-language program on a ch32v003 and run it on a supercomputer, but that probably won't be a useful thing to do in practice; rv32 and rv64 are incompatible enough to be problematic, and cramping your code to fit into 16 registers will compromise its performance on your supercomputer, not to mention not using isa extensions like v. and if you don't care about its performance on your supercomputer you might as well just use qemu