This was excellent debugging and a great write up. If the SHAREABLE bit is like on ARM, it won't effect a system running only one core. On some systems this ca

This was excellent debugging and a great write up. If the SHAREABLE bit is like on ARM, it won't effect a system running only one core. On some systems this causes memory ordering to that shareable IO memory to be ordered across multiple cores where it might not be otherwise. There's a performance trade off in that additional cache coherency traffic can be a bottleneck, but for something like a UART shouldn't be an issue and could be left shareable.