3 ms·
Fixed the UART Interrupt and Platform-Level Interrupt Controller (Ox64 BL808)
- johndoe0815 3y agoThe site seems to be down, but it was successfully mirrored at archive.org: https://web.archive.org/web/20231209230622/https://lupyuen.codeberg.page/articles/plic3.html https://web.archive.org/web/20231209230622/https://lupyuen.c... Edit: up and running again...
- rsaxvc 3y agoThis was excellent debugging and a great write up. If the SHAREABLE bit is like on ARM, it won't effect a system running only one core. On some systems this causes memory ordering to that shareable IO memory to be ordered across multiple cores where it might not be otherwise. There's a performance trade off in that additional cache coherency traffic can be a bottleneck, but for something like a UART shouldn't be an issue and could be left shareable.
- lupyuen 3y agoThis is very helpful, thank you so much!