I'm not entirely sure, but "physical memory" is a good guess - "PHAM XFER" and "BUS REQ" go to the BIU control logic, and "PHAM INPUT" to the EA latches. The b

I'm not entirely sure, but "physical memory" is a good guess - "PHAM XFER" and "BUS REQ" go to the BIU control logic, and "PHAM INPUT" to the EA latches. The boxes around the edge of the diagram represent the pins, COREQ being one of them. A few are normally left unconnected and only exist as test pads on the die. Mostly these are for ICE mode (what became System Management Mode on 386SLC and later CPUs). - ICES0# / ICES1# are used for bus control like S0# and S1# are outside of ICE mode. This is why the CPU appears to halt after executing opcode 0F 04 ("STOREALL", which enters ICE mode) - ICEBP# is the hardware signal to enter ICE mode, acting much like RESET# except that the state is saved to physical address 000800H (in the separate ICE memory space) - ICE31 / ICE20 are used to output a 4-bit length for the current instruction (on alternating clock cycles, since every instruction takes at least two) In addition to the diagram, there is the "detailed description of preferred embodiment" in the text, which doesn't explain what PHAM means, but documents for example how opcodes are decoded from the byte queue into a CROM entry point and fields for immediate operands etc. - this should be very similar on the 386, except for the byte queue being longer (16 instead of 6 bytes). The decoded queue ("INSTRUCTION FIFO CONTROL") is 3 instructions long on both chips, and the diagram shows the various fields with their bit lengths to the right of that box. For some reason the displacement is 17 bits, if that's not a typo then probably 33 on the 386? My guesses about the 5 single-bit flags grouped together: - W: byte/word access - LOCK: lock prefix - RPZ: REPZ/REPNZ - DIR: direction (from/to memory)? - USER: undocumented F1h prefix on 286? (not applicable to 386, which uses UMOV opcode for that purpose) For the 386 there are obviously going to be flags for 32-bit address and operand size in there. It also mentions that the microcode can notify the BIU to suspend prefetching before a memory access occurs, "LCN" and "WAIT" might have something to do with that.