4 ms·
I love it. Looks fairly well-rounded. I didn't see in the written artifacts: what's the effective instructions per second?
by quantified 3y ago
I love it. Looks fairly well-rounded.
I didn't see in the written artifacts: what's the effective instructions per second?
- B1FF_PSUVM 3y agoI checked https://en.wikipedia.org/wiki/7400-series_integrated_circuits https://en.wikipedia.org/wiki/7400-series_integrated_circuit... and gate delay (tpd) for 74HC is 15 ns. I wouldn't expect more than 1 MIPS, which is what the DEC VAX 11/780 was doing around 1980. (Awesome one-man project, if that's the case.)
- jacquesm 3y agoIf it gets 1 MIPS I'd be absolutely amazed, check out the size of the wire wrap boards: http://www.sol-1.org/images/sol/board-1.jpg http://www.sol-1.org/images/sol/board-1.jpg
- dboreham 3y agoThey're normal sized boards fwiw.
- kjs3 3y agoThose are Multibus-1 prototyping boards, so they'd be 12"x6.75". It's a good size for building non-trivial things.
- jacquesm 3y agoI didn't mean to imply that they are abnormal, just that they are large and large boards like that tend to be harder to make stable when using wire wrap as a technique. I've done this - and stacks of them too - but I've also spent days tracing a faulty wire, and the chance of such faults goes up as the number of wires goes up.
- marktangotango 3y agoWire length matching would seem to be a big factor in attaining the highest performance.