3 ms·
The program RAM is the columns of the LUTs, 64 bits/cell. The Data RAM is the latches of the data flowing through the LUTs, 4 bits/cell. I've thought it likel
by mikewarot 3y ago
The program RAM is the columns of the LUTs, 64 bits/cell.
The Data RAM is the latches of the data flowing through the LUTs, 4 bits/cell.
I've thought it likely that edge I/O would be best.
The debug tooling would ideally map everything as 2 chunks of RAM, program and state, thus allowing random I/O via a host CPU or DMA.
The major hurdle after that is software for compiling and routing, which I intend to build
My emulator runs at a good clip, 32 x 32 cells at about 35 khz, or 1024 x 1024 at about 16 hz. I haven't multi threaded it yet, but I can. That should give about 4x performance
Maybe an emulator library for the Arduino would be a good idea?
The Google chip shuttles should be a good way to get it implemented for real.