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BitGrid[1] is the most efficient general purpose compute architecture possible for Petaflops and beyond. It eliminates memory bandwidth issues. Its a nice el

BitGrid[1] is the most efficient general purpose compute architecture possible for Petaflops and beyond. It eliminates memory bandwidth issues. Its a nice elegant alternative architecture. I'm quite surprised nobody actually tried it earlier. [1] https://github.com/mikewarot/Bitgrid https://github.com/mikewarot/Bitgrid * I give 50/50 odds I'm a crackpot on this one... I'd really like to know for sure which way that coin toss comes out in the end

countWSS 3y ago
This is some sort of cellular automata, nothing crackpot about that, perhaps a FPGA demo with it would demonstrate the claims its a superior architecture. There are many exotic architectures like Transport-triggered, Computational RAM and async CPUs, but they're not easily implemented in hardware and claims of these exotics outperforming conventional CPUs didn't materialize.
RetroTechie 3y ago
> It eliminates memory bandwidth issues. About that: where is the RAM here? Some applications are compute-heavy, and BitGrid seems a nice architecture for that. But some applications are not. Where can they get/put their data? Btw... this screams for implementation on reasonably sized FPGA (say, 100k+ LUTs). The size to have a go at more interesting uses than "hello world" type ones. Any chance of doing that? A single cell in the grid looks simple enough. Plenty cheapo FPGA boards around.
- mikewarot 3y ago
  The program RAM is the columns of the LUTs, 64 bits/cell. The Data RAM is the latches of the data flowing through the LUTs, 4 bits/cell. I've thought it likely that edge I/O would be best. The debug tooling would ideally map everything as 2 chunks of RAM, program and state, thus allowing random I/O via a host CPU or DMA. The major hurdle after that is software for compiling and routing, which I intend to build My emulator runs at a good clip, 32 x 32 cells at about 35 khz, or 1024 x 1024 at about 16 hz. I haven't multi threaded it yet, but I can. That should give about 4x performance Maybe an emulator library for the Arduino would be a good idea? The Google chip shuttles should be a good way to get it implemented for real.

countWSS 3y ago

This is some sort of cellular automata, nothing crackpot about that, perhaps a FPGA demo with it would demonstrate the claims its a superior architecture. There are many exotic architectures like Transport-triggered, Computational RAM and async CPUs, but they're not easily implemented in hardware and claims of these exotics outperforming conventional CPUs didn't materialize.

RetroTechie 3y ago

> It eliminates memory bandwidth issues. About that: where is the RAM here? Some applications are compute-heavy, and BitGrid seems a nice architecture for that. But some applications are not. Where can they get/put their data? Btw... this screams for implementation on reasonably sized FPGA (say, 100k+ LUTs). The size to have a go at more interesting uses than "hello world" type ones. Any chance of doing that? A single cell in the grid looks simple enough. Plenty cheapo FPGA boards around.

mikewarot 3y ago
The program RAM is the columns of the LUTs, 64 bits/cell. The Data RAM is the latches of the data flowing through the LUTs, 4 bits/cell. I've thought it likely that edge I/O would be best. The debug tooling would ideally map everything as 2 chunks of RAM, program and state, thus allowing random I/O via a host CPU or DMA. The major hurdle after that is software for compiling and routing, which I intend to build My emulator runs at a good clip, 32 x 32 cells at about 35 khz, or 1024 x 1024 at about 16 hz. I haven't multi threaded it yet, but I can. That should give about 4x performance Maybe an emulator library for the Arduino would be a good idea? The Google chip shuttles should be a good way to get it implemented for real.