Core memory needs a lot of manual wiring, and you need two demultiplexers to address anything in it. Torsion wire delay line has no demultiplexer and is much si

Core memory needs a lot of manual wiring, and you need two demultiplexers to address anything in it. Torsion wire delay line has no demultiplexer and is much simpler; it's basically a coil of invar wire on a spacer, with some rubber dampeners, an actuator, and a sensor. And it's inherently serial, many early calculators had serial architectures built around acoustic or IC delay lines. > at the speeds they are targeting, I think delay lines might be difficult Speed of the torsional wave is around 3000-3500m/s depending on the alloy you use. You can make the coil about several dozen meters long before running into issues (practical torsion wire delay lines were 20 to 80m long). That would give 6 to 27ms of delay, which can keep 600 to 2700 bits in the loop at 100kHz, or 10 times more at 1MHz. The same amount of cores would be far more labor intensive to make.