>It would be interesting to compare the microcode. I've disassembled the microcode[1], it's similar to the 8086 but with some changes: - No subroutines are us

>It would be interesting to compare the microcode. I've disassembled the microcode[1], it's similar to the 8086 but with some changes: - No subroutines are used (effective address calculation and most of multiply/divide handled by dedicated logic). CORR is also no longer needed. - The 'update flags' bit now has a second function: on a jump, it causes the next micro-instruction to always be executed unconditionally (saving one clock cycle in case the jump is taken) - MOVS / INS / OUTS are optimized, using a special memory-to-memory (or I/O) transfer; the microcode for this has the 'IRQ' bit set. The address isn't loaded into IND for these anymore (tested it with LEA reg,reg) - maybe it's using the DMA controller? - Slightly different condition codes ("CX not zero" was added for LOOP/JCXZ; "segment prefix is present" for adjusting IP on interrupted string instructions). - Order of the 4 instructions in each 84-bit row is shuffled around for some reason [1] see https://news.ycombinator.com/item?id=34334799 https://news.ycombinator.com/item?id=34334799 and https://forum.vcfed.org/index.php?threads/8088-8086-microcode-disassembly.77933/page-2#post-951895 https://forum.vcfed.org/index.php?threads/8088-8086-microcod...