I was answering the parent remark which was about RISC-V. And my point is that if RISC-V achieves a significant amount of open designs and tooling then anyone

I was answering the parent remark which was about RISC-V. And my point is that if RISC-V achieves a significant amount of open designs and tooling then anyone who joins is roughly speaking guaranteed parity (in design - something like ISA and microarchitecture, not in foundry). Which is much better than the current situation.