The 8088 has a four-byte instruction queue, and at times when the data bus would otherwise be idle the bus interface unit will prefetch the next instruction byt

The 8088 has a four-byte instruction queue, and at times when the data bus would otherwise be idle the bus interface unit will prefetch the next instruction byte. So fetch and decode/execute are already overlapped. What really slows down the 8088 is that each 8-bit transfer on the data bus requires four clock cycles. That means simply fetching the two-byte instruction requires eight clocks! Instruction fetch is so slow on the 8088 that it's virtually impossible to achieve the published instruction timing.