You're right! I can think of two cases I've run into where bypassing the cache can be faster compared to a miss. On some caches the line must be filled before

You're right! I can think of two cases I've run into where bypassing the cache can be faster compared to a miss. On some caches the line must be filled before allowing a write(ignoring any write buffer at the interface above the cache) - those basically halve the memory bandwidth when writing to a lot of cache lines. Some systems now have instructions for filling a cache line directly to avoid this. And some CPUs have bit-per-byte validity tracking to avoid this too. Even on caches with hit-during-fill, a direct read from an address near the last-to-be-filled end of a cacheline can sometimes be a little faster than a cache miss, since the miss will fill the rest of the line first.