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They're more constrained by advanced packaging (CoWoS) capacity rather than the manufacturing of the silicon.
by tambre 3y ago
They're more constrained by advanced packaging (CoWoS) capacity rather than the manufacturing of the silicon.
- tyfighter 3y agoBut from the pictures, the Maia 100 is also using CoWoS packaging. That will be necessary for any new HBM chip.
- localhost 3y agoThe latest Stratechery interview had Pat Gelsinger on it and he was talking about how Intel is happy to package up TSMC dies in their foundries. Relevant quote: > So it really brings together many of the things that Intel is doing as an IDM, now bringing it together in a heterogeneous environment where we’re taking TSMC dies. We’re going to be using other foundries in the industry, we’re standardizing that with UCIe. So I really see ourself as the front end of this multi-chip chiplet world doing so in the Intel way, standardizing it for the industry’s participation with UCIE, and then just winning a better technology.