>it doesn’t seem like they take instruction fusion into account It is not mandatory. Not considering fusion means we are looking at the worst case scenario fo

>it doesn’t seem like they take instruction fusion into account It is not mandatory. Not considering fusion means we are looking at the worst case scenario for RISC-V, that is, a longer-looking path of non-fused yet typically fusable pairs. Since even then RISC-V is looking no worse than ARM (even slightly better!), this is a very positive result for RISC-V.