The ISA is variable length/scalable, but this implementation uses a 4096 wide register file. They are a bit disingenuous in claiming they support rvv 1.0 while

The ISA is variable length/scalable, but this implementation uses a 4096 wide register file. They are a bit disingenuous in claiming they support rvv 1.0 while others only a subset, as they haven't implemented vrgather or vcompress yet, but there are open pull request for them [0]. Sadly there also seem to be a few bugs when simulating with verilator [1], so I couldn't measure all instructions, but here is `vadd.vv` and `vwaddu.vv` for the VLEN=4096, four lane configuration: vadd.vv: e32m1: 16 cycles e32m2 32 cycles e32m4 63 cycles e32m8 126 cycles vwaddu.vv: e32m1: 34 cycles e32m2: 69 cycles e32m4: 140 cycles I don't have the time to rebuild ara now, but the 16 lane configuration should roughly be four times faster. [0] https://github.com/pulp-platform/ara/pull/180 https://github.com/pulp-platform/ara/pull/180 [1] https://github.com/pulp-platform/ara/issues/250 https://github.com/pulp-platform/ara/issues/250