4 ms·

I don’t really know what to make of this article. On one hand, it’s an interesting study of a theoretical IPC limit on some real codes. On the other hand, I do

by ribit 3y ago

I don’t really know what to make of this article. On one hand, it’s an interesting study of a theoretical IPC limit on some real codes. On the other hand, I don’t believe authors manage to show what they claim to show: - it doesn’t seem like they take instruction fusion into account (a common technique used to break frequently occurring serial dependencies) - the ideal CPU model does not estimate the boundary conditions needed to achieve the same performance with either ISA; the relevant question question is whether simpler RISC-V instructions mean that more decoders/EUs are needed or whether fusion can equalize the difference Is this a peer-reviewed publication?

snvzz 3y ago
>it doesn’t seem like they take instruction fusion into account It is not mandatory. Not considering fusion means we are looking at the worst case scenario for RISC-V, that is, a longer-looking path of non-fused yet typically fusable pairs. Since even then RISC-V is looking no worse than ARM (even slightly better!), this is a very positive result for RISC-V.