3 ms·
>ARM 64 gets this right, with fixed length 32 bit instructions. At the expense of code density, yet RISC-V is easy to decode, with implementations going up to
by snvzz 3y ago
>ARM 64 gets this right, with fixed length 32 bit instructions.
At the expense of code density, yet RISC-V is easy to decode, with implementations going up to 12-way decode (Veyron V2) despite variable length.
ARM64 hardly "gets it right".
- camel-cdr 3y agoI wouldn't say ARM64 gets it wrong either, I think both are viable approaches.
- snvzz 3y agoBoth approaches are viable, but RISC-V's approach is better, as it provides higher code density without imposing a significant increase in complexity in exchange. Higher code density is valuable. E.g.: - The decoders can see more by looking at a window of code of the same size, or we can have a narrowed window. - We can have less cache and save area and power. We can also clock the cache higher, enabled by it being smaller, lowering latency cycles. - Smaller binaries or rom image. Soon to be available (2024) large, high performance implementations will demonstrate RISC-V advantages well.