3 ms·
There seems to be some confusion in the replies to your post. What I’ve read is that DDR5 has “on-die ECC” which means that the module itself handles the error
by AlbertoGP 3y ago
There seems to be some confusion in the replies to your post.
What I’ve read is that DDR5 has “on-die ECC” which means that the module itself handles the error correction, but then it can not handle errors that happen in transit to the CPU as full ECC can.
There are DDR5 full-ECC modules that would be real equivalents to DDR4 ECC.
> When the latest version of DDR memory – DDR5 – was introduced in 2020, marketing campaigns
got one important fact wrong. DDR5 UDIMM, the regular desktop RAM we’re all familiar with,
was touted as having “built-in” Error Correcting Code (ECC). Not true. What it has is built-in data
checking, which is a very different feature that shouldn’t be confused with traditional ECC.
For that, your customers will need DDR5 ECC UDIMM memory.
— Intel, “Error Correcting Code (ECC)
vs. Built-in Data Checking”: https://www.intel.com/content/www/us/en/content-details/754991/ecc-memory-vs-ddr5-built-in-data-checking-infographic.html https://www.intel.com/content/www/us/en/content-details/7549...
- wtallis 3y agoAdditionally, on-die ECC isn't unique to DDR5; it's a necessity for any DRAM built on the most recent high-density fab processes. It was used for at least some LPDDR4 memories, and probably most or all LPDDR5.
- jakobson14 3y agoCan't wait to see another round of rowhammer papers trashing these things. XD
- dazed_confused 3y agoRow and col lines are so close nowadays; you are fighting physics... Older processes didn't have this problem due to row isolation.
- jakobson14 3y agoIt's not the selection lines, up on higher metal layers. It's the actual memory cells themselves being too close together on the substrate.
- jacquesm 3y agoThat's mostly because otherwise they wouldn't be reliable enough to use.
- deleted 3y ago[deleted]