> Part of the rumour for some Celeron chips Not a rumor. Starting with Coppermine, Celerons were Binned P3s. Same die size and all. Interestingly, AMD did not

> Part of the rumour for some Celeron chips Not a rumor. Starting with Coppermine, Celerons were Binned P3s. Same die size and all. Interestingly, AMD did not typically do the same for the Duron (with one or two exceptions). My understanding at the time was their dies had extra cache to handle defects without full binning.