3 ms·
My Retro-socket3-toy-unit with a P83@100 MHz is fast (40MHz bus), but the DX5x86@150mhz (50MHz bus) beats everything except in quake. Timings aren't that great
by consp 3y ago
My Retro-socket3-toy-unit with a P83@100 MHz is fast (40MHz bus), but the DX5x86@150mhz (50MHz bus) beats everything except in quake. Timings aren't that great for the memory but the synchronous PCI bus (and working PCI VGA card at that speed) beats everything you throw at it.
- mobilio 3y agoSame here - all DOS games was faster on DX4, but Pentium was so smooth on Quake.
- TerrifiedMouse 3y agoCarmack and Abrash optimized the heck out of Quake making use of a “quirk” in the Pentium where you can overlap integer operations and floating point DIV to eke out every last drop of performance. Unfortunately the trick doesn’t work on early AMD K5/6 nor Cyrix CPUs - although Cyrix CPUs probably had other more serious problems. https://youtu.be/DWVhIvZlytc?si=DBE9zpTLj_16-GAt https://youtu.be/DWVhIvZlytc?si=DBE9zpTLj_16-GAt
- Sharlin 3y agoYeah. Their perspective correct texture mapping did a perspective div only every 16 pixels drawn – in itself a considerable optimization with almost imperceptible loss in quality – but the big deal was that on the Pentium specifically, the integer pipeline could be almost perfectly cycle-optimized to process sixteen pixels in the time the FPU executed the next perspective division in parallel so the result was ready just as it was needed!
- touisteur 3y agoMore on this in the Black Book graphic shttps://news.ycombinator.com/item?id=35738709 https://news.ycombinator.com/item?id=35738709 . Programming on Pentium is towards the end.
- rasz 3y agoK5/Cyrix could overlap Integer and FPU operations, what they couldnt do was interleave (pipeline) FPU operations so that multiple floating point instructions ran in parallel. https://www.phatcode.net/res/224/files/html/ch63/63-02.html https://www.phatcode.net/res/224/files/html/ch63/63-02.html Here a non perspective correction related Quake FPU code example https://github.com/id-Software/Quake/blob/bf4ac424ce754894ac8f1dae6a3981954bc9852d/QW/client/r_drawa.asm#L259 https://github.com/id-Software/Quake/blob/bf4ac424ce754894ac... Lcliploop: fld ds:dword ptr[0+0+esi] fmul ds:dword ptr[0+0+ebx] fld ds:dword ptr[0+4+esi] fmul ds:dword ptr[0+4+ebx] fld ds:dword ptr[0+8+esi] fmul ds:dword ptr[0+8+ebx] fxch st(1) faddp st(2),st(0) fld ds:dword ptr[0+0+edx] fmul ds:dword ptr[0+0+ebx] fld ds:dword ptr[0+4+edx] fmul ds:dword ptr[0+4+ebx] fld ds:dword ptr[0+8+edx] fmul ds:dword ptr[0+8+ebx] fxch st(1) faddp st(2),st(0) fxch st(3) faddp st(2),st(0) faddp st(2),st(0) fsub ds:dword ptr[12+ebx] fxch st(1) fsub ds:dword ptr[12+ebx] fxch st(1) fstp ds:dword ptr[Ld0] fstp ds:dword ptr[Ld1] FXCH instruction is free (zero cycles) on Pentium for most instruction combinations, AMD caught up in late 1998 with CXT revision K6-2. http://www.azillionmonkeys.com/qed/cpuwar.html http://www.azillionmonkeys.com/qed/cpuwar.html