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I'll bought the same board, and am somewhat disappointed by this news. Do you happen to have the name of the gcc branch on hand so I can get that going when the

I'll bought the same board, and am somewhat disappointed by this news. Do you happen to have the name of the gcc branch on hand so I can get that going when the thing arrives?

camel-cdr 3y ago
I've been using the one archived by bruce hoult: https://github.com/brucehoult/riscv-gnu-toolchain https://github.com/brucehoult/riscv-gnu-toolchain It doesn't support autovectorization though. Together with some assembly macros to allow writing in a subset of rvv 1.0 that also works on rvv 0.7.1 (source compatible, but not binary compatible. [0] There is also the xuantie toolchain that does support intrinsic and some sort of autovectorization, I think. But I haven't used that one, and it won't be as good as upstream gcc/llvm. [1] [0] https://github.com/camel-cdr/rvv-bench/blob/main/thirdparty/rvv-rollback.S https://github.com/camel-cdr/rvv-bench/blob/main/thirdparty/... [1] https://github.com/T-head-Semi/xuantie-gnu-toolchain https://github.com/T-head-Semi/xuantie-gnu-toolchain
- MrDrMcCoy 3y ago
  Thanks!
brucehoult 3y ago
That shouldn't be news. Other than the CanMV-K230 (Kendryte K230, single 1.6 GHz C908 core implementing RVV) which just started shipping in the last two weeks, every RISC-V board with RVV has either C906 or C910 cores which implement draft 0.7.1. Those CPU cores were announced in mid 2019 (when RVV 0.7.1 was the current draft) and boards using them start arriving in mid to late 2021. RVV 1.0 boards will start arriving in force next year, probably starting with the StarFive JH8110 SoC, and (apparently, though I'm not sure I believe it) an update of the SG2042 in the Pioneer, and also the 16 core (but faster cores) SG2380. > Do you happen to have the name of the gcc branch The branch has been deleted from the official repo. I have a snapshot on my github: https://github.com/brucehoult/riscv-gnu-toolchain https://github.com/brucehoult/riscv-gnu-toolchain Note that it is primarily binutils which understands RVV 0.7.1. GCC understands it only to the extent of accepting "v" in "-march" and passing the right flags to the assembler. This enables using the gcc driver to build .s files and inline RVV asm in C. There is no support for RVV intrinsic functions or auto-vectorisation. It's also a somewhat old gcc. I use it to build .o files from assembly language, and then link them with C compiled by a newer gcc or llvm. Or not, most of the time gcc 9 is fine. THead have RVV 0.7.1 support in newer gcc, but I haven't been tracking that closely.

I'll bought the same board, and am somewhat disappointed by this news. Do you happen to have the name of the gcc branch on hand so I can get that going when the thing arrives?

camel-cdr 3y ago

I've been using the one archived by bruce hoult: https://github.com/brucehoult/riscv-gnu-toolchain https://github.com/brucehoult/riscv-gnu-toolchain It doesn't support autovectorization though. Together with some assembly macros to allow writing in a subset of rvv 1.0 that also works on rvv 0.7.1 (source compatible, but not binary compatible. [0] There is also the xuantie toolchain that does support intrinsic and some sort of autovectorization, I think. But I haven't used that one, and it won't be as good as upstream gcc/llvm. [1] [0] https://github.com/camel-cdr/rvv-bench/blob/main/thirdparty/rvv-rollback.S https://github.com/camel-cdr/rvv-bench/blob/main/thirdparty/... [1] https://github.com/T-head-Semi/xuantie-gnu-toolchain https://github.com/T-head-Semi/xuantie-gnu-toolchain

MrDrMcCoy 3y ago
Thanks!

brucehoult 3y ago

That shouldn't be news. Other than the CanMV-K230 (Kendryte K230, single 1.6 GHz C908 core implementing RVV) which just started shipping in the last two weeks, every RISC-V board with RVV has either C906 or C910 cores which implement draft 0.7.1. Those CPU cores were announced in mid 2019 (when RVV 0.7.1 was the current draft) and boards using them start arriving in mid to late 2021. RVV 1.0 boards will start arriving in force next year, probably starting with the StarFive JH8110 SoC, and (apparently, though I'm not sure I believe it) an update of the SG2042 in the Pioneer, and also the 16 core (but faster cores) SG2380. > Do you happen to have the name of the gcc branch The branch has been deleted from the official repo. I have a snapshot on my github: https://github.com/brucehoult/riscv-gnu-toolchain https://github.com/brucehoult/riscv-gnu-toolchain Note that it is primarily binutils which understands RVV 0.7.1. GCC understands it only to the extent of accepting "v" in "-march" and passing the right flags to the assembler. This enables using the gcc driver to build .s files and inline RVV asm in C. There is no support for RVV intrinsic functions or auto-vectorisation. It's also a somewhat old gcc. I use it to build .o files from assembly language, and then link them with C compiled by a newer gcc or llvm. Or not, most of the time gcc 9 is fine. THead have RVV 0.7.1 support in newer gcc, but I haven't been tracking that closely.