The DRAM chips themselves are asynchronous (there's no clock signal connected to the RAM chip), however they expect a sequence of operations with specific timin

The DRAM chips themselves are asynchronous (there's no clock signal connected to the RAM chip), however they expect a sequence of operations with specific timings in order to work. The PET's solution was to create a small synchronous circuit to generate the control signals with the correct timings for the DRAM. This however wasn't the only way it could be done, as the other answer states how the PC/XT did it with delay lines.