2 ms·

No, not inherently. The point is that simplicity and elegance enables efficiency.

• mannyv 3y ago
  Enables, but does not guarantee. The PPC ISA is simple, but the POWER chips themsleves were never designed for power efficiency. Likewise the ARM ISA is now associated with power efficiency, but there's nothing in the ISA itself that mandates power efficiency. In fact, I'll bet a clever chip designer could design an x86 (or x86_64) chip that was low power. That would be a killer exercise. I want to say some of the third party licensees tried to do that with their x86 SoCs a long time ago. They failed for different reasons.
  • brucehoult 3y ago
    The PPC ISA is huge, with a vast number of instructions (hundreds), which implies a lot of energy-sucking decoder circuitry -- and data path too. RISC-V allows tiny designs with just 37 instructions. ARMv6-M aka Thumb 1 (plus CSR instructions) is also fairly minimal, though not as much as RV32I.
    • RetroTechie 3y ago
      > The PPC ISA is huge, with a vast number of instructions (hundreds), which implies a lot of energy-sucking decoder circuitry -- and data path too. Not necessarily. It depends on how regular (orthogonal) the instruction formats are. Highly regular (few formats) = easy to decode even if there are many instructions. But for example x86 has many different instruction formats and -lengths. Decoding all those does come at a cost. RISC-V is very good in this regard. There's even "embedded" variants that drop half the register set (RV64E, which imho doesn't make much sense, and RV32E which does). And there's some projects having a go at designing a 16-bit variety (to compete with legacy 8-bit ISAs perhaps?). Remains to be seen if that ever becomes a standard though.