Hardware divide has little to do with it. Historically, it is just the register width. Division is too complex and variable even within an ISA. On a side note,

Hardware divide has little to do with it. Historically, it is just the register width. Division is too complex and variable even within an ISA. On a side note, there are still micros in common use today, such as low end Cortex that don't have any hardware divider. And the lifecycles of embedded devices mean that even older architectures, but still less than 20 years old such as ARMv5 without hardware dividers are still being maintained. It's not that historic. The performance of hardware divide isn't something that follows simply from the "natural" register width of the processor anyway, it depends on the real estate and implementation given to it. > I think older processors didn't have say a divide instruction at a bunch of different widths But the common ones did, for example PPC and even the 8086. The reason for this is because division is slow and you get a benefit by using the smallest width possible. > special width that was one-to-one with underlying instructions That's usually just the width of the general purpose registers. Of course 64-bit came along and threw this out the window.