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You're welcome. I'm a physical design engineer. This is what I do https://en.wikipedia.org/wiki/Physical_design_(electronics) https://en.wikipedia.org/wiki/P
by lizknope 3y ago
You're welcome. I'm a physical design engineer. This is what I do
https://en.wikipedia.org/wiki/Physical_design_(electronics) https://en.wikipedia.org/wiki/Physical_design_(electronics)
This is the program I use everyday. It has a list price of over $1 million for a single license. My company has about 800 licenses but we probably get discounts of 60%
https://www.cadence.com/en_US/home/tools/digital-design-and-signoff/soc-implementation-and-floorplanning/innovus-implementation-system.html https://www.cadence.com/en_US/home/tools/digital-design-and-...
https://www.youtube.com/watch?app=desktop&v=TDvq1hVXzRc https://www.youtube.com/watch?app=desktop&v=TDvq1hVXzRc
- gosub100 3y agoI worked at ASML San Diego for about a year as a bottom-rank software engineer (contractor) for 7nm. The scale and complexity of the thing was mind blowing. I worked on the seed laser team, alongside the team that did the molten-tin gun. I think that domain is a rare case where the users (people like you) have a higher knowledge burden than the manufacturer. I can't imagine what actually goes on (in Taiwan and elsewhere) to actually use the machines and sign off the wafers as good-to-go.
- lizknope 3y agoThat is really cool. I've been in the industry for over 25 years and I've never been to a fab. The number of jobs and specialization is so high that you need thousands of experts in their area but they have little knowledge about someone else's job. I know very little about all the equipment used to make chips. The people next to me that write Verilog know very little about DRC violations that I described. It takes a team of thousands of engineers to make this stuff.