5 ms·

> if you need more current why not use a thicker wire and only have 2 How do you route that current in one pin to the two locations the two pins handled? You'v

> if you need more current why not use a thicker wire and only have 2 How do you route that current in one pin to the two locations the two pins handled? You've just moved the point where the split happens from on the motherboard to on the chip package.

gosub100 3y ago
you could have 2 bus bars around all 4 sides of the CPU, and tap off them at the point where the die has its connectors to the "body" (enclosure?) of the package. All the die pics I've seen, the tiny gold signal wires still route around the edges (i.e. they don't join the die in the center). So a thicker bus should work for the main voltage supply. But as the sibling commenter said, it has to do with signal impedance.
- lizknope 3y ago
  You are looking at wire bonded chips. Wire bonding is still used for chips in older process nodes and lower number of IO. This article says up to 800 IOs https://semiengineering.com/wirebond-technology-rolls-on/ https://semiengineering.com/wirebond-technology-rolls-on/ But all the high performance chips in leading edge process nodes like 3nm are flip chips. The last time I worked on a wire bond chip was in 130nm in 2004. With a wire bond chip you can only have IO for signals and power/ground around the periphery. Some wire bond chips have 2 rings of IO pads but it makes the wire bond angles complicated. It's difficult to jump over other wire bonds to get closer to the center. https://en.wikipedia.org/wiki/Flip_chip https://en.wikipedia.org/wiki/Flip_chip Flip chips have a series of bumps above the top layer of the chip. These bumps are then connected to a small PCB inside a package or some other kind of interposer. The transistors are on the bottom of the die and then up to 18 layers of metal are built on top. In a wire bond chip the heat has to go up through all that metal stackup which is usually encased in a glob top which isn't great for heat transfer. https://www.gluespec.com/blog/glob-top-encapsulation https://www.gluespec.com/blog/glob-top-encapsulation In contrast a flip chip has the die mounted upside with the top layer mounted to the PCB and the side with transistors is on top and can be directly mounted to a heat sink. Intel and AMD used to have bare die around 2000 but then mounted heat spreaders on top because sometimes people would mount the heat sink incorrectly and crack the corner of the die when tightening down non-uniformly. http://mantravlsi.blogspot.com/2014/10/flip-chip-and-wire-bonding.html http://mantravlsi.blogspot.com/2014/10/flip-chip-and-wire-bo... With a flip chip we can have over 15,000 IO in the chip. The flip chip bumps can be all over the die not just the periphery. Not only can we put IO in the center but the density of the bumps can be much higher compared to the pad points where a wire bonder would attach. As for your original question about some kind of continuous bar shaped contact we have a power grid underneath on every layer to distribute the power across the chip. This has to go from the top layer Metal18 down through vias to the transistors below Metal1. Modern chips have multiple voltages in multiple voltage domains. The DDR and PCIE sections have their own voltage requirements. The standard cells that are the combination logic within a CPU operate on much lower voltages. We have dynamic voltage control where the voltage is lowered to save power. We have voltage islands where the USB port can be shut off if nothing is plugged in or CPU core 1 is active while cores 2-4 are off saving power. This requires dedicated power / ground bumps and head switches to disconnect power to sections of the chip. I don't think we could manufacture your concept of a "bar shaped contact" because the process DRC (Design Rule Check) stuff is very rigid about what can be manufactured. Certain shapes, widths, and turns decrease the yield so they aren't allowed. https://www.vlsi-expert.com/2014/12/design-rule-check.html https://www.vlsi-expert.com/2014/12/design-rule-check.html
  - dmvdoug 3y ago
    Stupid question: is “bump” the actual name for the bumps you talk about or is there some tricked out fancy name for them? (Curiosity only.)
    - lizknope 3y ago
      Yes, "bump" is the actual technical name. You can click on the wikipedia link I posted to flip chip. You can see a diagram here of the layer stack up. You can see that the solder bump on the top that connects to the outside world is huge compared to the internal metal layers. https://en.wikipedia.org/wiki/Back_end_of_line https://en.wikipedia.org/wiki/Back_end_of_line A standard cell in 5nm is around 200nm in height. The width can vary but this way all the cells go together like Lego bricks. Each metal layer going up from Metal1 to the top gets wider and thicker. By the time you get up to Metal18 or so it is probably 20 times wider and thicker than M1. This is useful because those upper layer metals distribute the power and ground and a chip wide clocks. The large top layer metal is also required for the huge bumps above that connect to the outside world. I think the current minimum bump pitch is around 130 microns. You can see these with your eye and don't need a microscope. Do the math on a chip that is 25mm by 25mm and a pitch of 130 microns and you can determine how many bumps you could fit on the chip.
  - gosub100 3y ago
    I wish I could give you more than just a "thank you", I love learning stuff like this, and I appreciate you explaining it in detail.
    - lizknope 3y ago
      You're welcome. I'm a physical design engineer. This is what I do https://en.wikipedia.org/wiki/Physical_design_(electronics) https://en.wikipedia.org/wiki/Physical_design_(electronics) This is the program I use everyday. It has a list price of over $1 million for a single license. My company has about 800 licenses but we probably get discounts of 60% https://www.cadence.com/en_US/home/tools/digital-design-and-signoff/soc-implementation-and-floorplanning/innovus-implementation-system.html https://www.cadence.com/en_US/home/tools/digital-design-and-... https://www.youtube.com/watch?app=desktop&v=TDvq1hVXzRc https://www.youtube.com/watch?app=desktop&v=TDvq1hVXzRc

gosub100 3y ago

you could have 2 bus bars around all 4 sides of the CPU, and tap off them at the point where the die has its connectors to the "body" (enclosure?) of the package. All the die pics I've seen, the tiny gold signal wires still route around the edges (i.e. they don't join the die in the center). So a thicker bus should work for the main voltage supply. But as the sibling commenter said, it has to do with signal impedance.

lizknope 3y ago
You are looking at wire bonded chips. Wire bonding is still used for chips in older process nodes and lower number of IO. This article says up to 800 IOs https://semiengineering.com/wirebond-technology-rolls-on/ https://semiengineering.com/wirebond-technology-rolls-on/ But all the high performance chips in leading edge process nodes like 3nm are flip chips. The last time I worked on a wire bond chip was in 130nm in 2004. With a wire bond chip you can only have IO for signals and power/ground around the periphery. Some wire bond chips have 2 rings of IO pads but it makes the wire bond angles complicated. It's difficult to jump over other wire bonds to get closer to the center. https://en.wikipedia.org/wiki/Flip_chip https://en.wikipedia.org/wiki/Flip_chip Flip chips have a series of bumps above the top layer of the chip. These bumps are then connected to a small PCB inside a package or some other kind of interposer. The transistors are on the bottom of the die and then up to 18 layers of metal are built on top. In a wire bond chip the heat has to go up through all that metal stackup which is usually encased in a glob top which isn't great for heat transfer. https://www.gluespec.com/blog/glob-top-encapsulation https://www.gluespec.com/blog/glob-top-encapsulation In contrast a flip chip has the die mounted upside with the top layer mounted to the PCB and the side with transistors is on top and can be directly mounted to a heat sink. Intel and AMD used to have bare die around 2000 but then mounted heat spreaders on top because sometimes people would mount the heat sink incorrectly and crack the corner of the die when tightening down non-uniformly. http://mantravlsi.blogspot.com/2014/10/flip-chip-and-wire-bonding.html http://mantravlsi.blogspot.com/2014/10/flip-chip-and-wire-bo... With a flip chip we can have over 15,000 IO in the chip. The flip chip bumps can be all over the die not just the periphery. Not only can we put IO in the center but the density of the bumps can be much higher compared to the pad points where a wire bonder would attach. As for your original question about some kind of continuous bar shaped contact we have a power grid underneath on every layer to distribute the power across the chip. This has to go from the top layer Metal18 down through vias to the transistors below Metal1. Modern chips have multiple voltages in multiple voltage domains. The DDR and PCIE sections have their own voltage requirements. The standard cells that are the combination logic within a CPU operate on much lower voltages. We have dynamic voltage control where the voltage is lowered to save power. We have voltage islands where the USB port can be shut off if nothing is plugged in or CPU core 1 is active while cores 2-4 are off saving power. This requires dedicated power / ground bumps and head switches to disconnect power to sections of the chip. I don't think we could manufacture your concept of a "bar shaped contact" because the process DRC (Design Rule Check) stuff is very rigid about what can be manufactured. Certain shapes, widths, and turns decrease the yield so they aren't allowed. https://www.vlsi-expert.com/2014/12/design-rule-check.html https://www.vlsi-expert.com/2014/12/design-rule-check.html
- dmvdoug 3y ago
  Stupid question: is “bump” the actual name for the bumps you talk about or is there some tricked out fancy name for them? (Curiosity only.)
  - lizknope 3y ago
    Yes, "bump" is the actual technical name. You can click on the wikipedia link I posted to flip chip. You can see a diagram here of the layer stack up. You can see that the solder bump on the top that connects to the outside world is huge compared to the internal metal layers. https://en.wikipedia.org/wiki/Back_end_of_line https://en.wikipedia.org/wiki/Back_end_of_line A standard cell in 5nm is around 200nm in height. The width can vary but this way all the cells go together like Lego bricks. Each metal layer going up from Metal1 to the top gets wider and thicker. By the time you get up to Metal18 or so it is probably 20 times wider and thicker than M1. This is useful because those upper layer metals distribute the power and ground and a chip wide clocks. The large top layer metal is also required for the huge bumps above that connect to the outside world. I think the current minimum bump pitch is around 130 microns. You can see these with your eye and don't need a microscope. Do the math on a chip that is 25mm by 25mm and a pitch of 130 microns and you can determine how many bumps you could fit on the chip.
- gosub100 3y ago
  I wish I could give you more than just a "thank you", I love learning stuff like this, and I appreciate you explaining it in detail.
  - lizknope 3y ago
    You're welcome. I'm a physical design engineer. This is what I do https://en.wikipedia.org/wiki/Physical_design_(electronics) https://en.wikipedia.org/wiki/Physical_design_(electronics) This is the program I use everyday. It has a list price of over $1 million for a single license. My company has about 800 licenses but we probably get discounts of 60% https://www.cadence.com/en_US/home/tools/digital-design-and-signoff/soc-implementation-and-floorplanning/innovus-implementation-system.html https://www.cadence.com/en_US/home/tools/digital-design-and-... https://www.youtube.com/watch?app=desktop&v=TDvq1hVXzRc https://www.youtube.com/watch?app=desktop&v=TDvq1hVXzRc