5 ms·

Copper was not always easy to work with in semiconductor chips. When I started in the industry in the 1990's all the wiring was aluminum. Articles about coppe

Copper was not always easy to work with in semiconductor chips. When I started in the industry in the 1990's all the wiring was aluminum. Articles about copper for wiring were research projects and which company would be the first to get it to mass production. IBM was the first in 1997 and then others followed. https://en.wikipedia.org/wiki/Copper_interconnects https://en.wikipedia.org/wiki/Copper_interconnects That's how technology is. Things start out hard and with a lot of work and time we invent new methods. Aluminum was once worth more than gold. Then we invented new processes of extraction and refinement. https://clintonaluminum.com/aluminum-was-once-worth-more-than-gold-and-silver/ https://clintonaluminum.com/aluminum-was-once-worth-more-tha...

magicalhippo 3y ago
Asianometry recently released a nice video[1] going into the transition to copper interconnects. [1]: https://www.youtube.com/watch?v=XHrQ-Pmvwao https://www.youtube.com/watch?v=XHrQ-Pmvwao
gosub100 3y ago
Can I ask an un-related question? In a CPU with thousands of pins, how come they use N pins for ground, N pins for VCC, when it seems simpler to have continuous bar-shaped contacts? Then pins would only be necessary for signals that actually changed. I see this in computer power supplies as well, they use N separate wires to carry V+ and N more for GND, but if you need more current why not use a thicker wire and only have 2?
- dmoy 3y ago
  > In a CPU with thousands of pins, how come they use N pins for ground, N pins for VCC, when it seems simpler to have continuous bar-shaped contacts? I can't speak to cpus with thousands of pins, but with significantly smaller chips that often have N>1 vcc or ground, it's typically due to layout convenience. The multiple vcc may be on e.g. opposite sides of the chip, and that makes it easier to route a pure vcc signal to a spot that needs it. It's easier to route outside the chip than inside the chip, because there's more space.
  - mrWiz 3y ago
    Additionally, there's also a benefit to standardization. Adding different pin styles makes the part harder to design and manufacture.
- Thetawaves 3y ago
  This improves the impedance of high speed signal transmission - at high speeds the currents want to flow through the ground path as close to the signal path as is possible. Said another way - designers work to reduce the total area inside the electric circuit to support high switching speeds. The additional power pins in high pin count chips serve to reduce the distance between high speed signal paths and their return ground paths. This is actually true for both ground and vcc, but is easier to visualize when working with signals and their grounds.
- undersuit 3y ago
  > if you need more current why not use a thicker wire and only have 2 How do you route that current in one pin to the two locations the two pins handled? You've just moved the point where the split happens from on the motherboard to on the chip package.
  - gosub100 3y ago
    you could have 2 bus bars around all 4 sides of the CPU, and tap off them at the point where the die has its connectors to the "body" (enclosure?) of the package. All the die pics I've seen, the tiny gold signal wires still route around the edges (i.e. they don't join the die in the center). So a thicker bus should work for the main voltage supply. But as the sibling commenter said, it has to do with signal impedance.
    - lizknope 3y ago
      You are looking at wire bonded chips. Wire bonding is still used for chips in older process nodes and lower number of IO. This article says up to 800 IOs https://semiengineering.com/wirebond-technology-rolls-on/ https://semiengineering.com/wirebond-technology-rolls-on/ But all the high performance chips in leading edge process nodes like 3nm are flip chips. The last time I worked on a wire bond chip was in 130nm in 2004. With a wire bond chip you can only have IO for signals and power/ground around the periphery. Some wire bond chips have 2 rings of IO pads but it makes the wire bond angles complicated. It's difficult to jump over other wire bonds to get closer to the center. https://en.wikipedia.org/wiki/Flip_chip https://en.wikipedia.org/wiki/Flip_chip Flip chips have a series of bumps above the top layer of the chip. These bumps are then connected to a small PCB inside a package or some other kind of interposer. The transistors are on the bottom of the die and then up to 18 layers of metal are built on top. In a wire bond chip the heat has to go up through all that metal stackup which is usually encased in a glob top which isn't great for heat transfer. https://www.gluespec.com/blog/glob-top-encapsulation https://www.gluespec.com/blog/glob-top-encapsulation In contrast a flip chip has the die mounted upside with the top layer mounted to the PCB and the side with transistors is on top and can be directly mounted to a heat sink. Intel and AMD used to have bare die around 2000 but then mounted heat spreaders on top because sometimes people would mount the heat sink incorrectly and crack the corner of the die when tightening down non-uniformly. http://mantravlsi.blogspot.com/2014/10/flip-chip-and-wire-bonding.html http://mantravlsi.blogspot.com/2014/10/flip-chip-and-wire-bo... With a flip chip we can have over 15,000 IO in the chip. The flip chip bumps can be all over the die not just the periphery. Not only can we put IO in the center but the density of the bumps can be much higher compared to the pad points where a wire bonder would attach. As for your original question about some kind of continuous bar shaped contact we have a power grid underneath on every layer to distribute the power across the chip. This has to go from the top layer Metal18 down through vias to the transistors below Metal1. Modern chips have multiple voltages in multiple voltage domains. The DDR and PCIE sections have their own voltage requirements. The standard cells that are the combination logic within a CPU operate on much lower voltages. We have dynamic voltage control where the voltage is lowered to save power. We have voltage islands where the USB port can be shut off if nothing is plugged in or CPU core 1 is active while cores 2-4 are off saving power. This requires dedicated power / ground bumps and head switches to disconnect power to sections of the chip. I don't think we could manufacture your concept of a "bar shaped contact" because the process DRC (Design Rule Check) stuff is very rigid about what can be manufactured. Certain shapes, widths, and turns decrease the yield so they aren't allowed. https://www.vlsi-expert.com/2014/12/design-rule-check.html https://www.vlsi-expert.com/2014/12/design-rule-check.html
- exmadscientist 3y ago
  I've never seen it on large logic chips, but this is pretty common on power ICs. Look up TI's HotRod QFNs for a particularly well-marketed example. Of course, the fab processes here are basically stone-age (for example, 0.6um BCD is still very common), so such things are easier to do and more beneficial for high-power parts.
adhesive_wombat 3y ago
Perhaps not trivial in chip interconnects, but it's fairly abundant and a rather workable material in general (hence the bronze age). Faraday probably wouldn't have gotten very far if copper was a gas at room temperature or only occured in trace amounts and there were no other ductile, solid conductive materials on Earth.
- lazide 3y ago
  Sure, though carbon and salt water is also reasonably conductive. Power distribution via hydraulics instead?
undersuit 3y ago
I think they're talking about copper electrical wiring not semiconductor use. If we couldn't use simple copper to bootstrap our energy intensive aluminum industry in the 1800s we might be using rhodium.

magicalhippo 3y ago

Asianometry recently released a nice video[1] going into the transition to copper interconnects. [1]: https://www.youtube.com/watch?v=XHrQ-Pmvwao https://www.youtube.com/watch?v=XHrQ-Pmvwao

gosub100 3y ago

Can I ask an un-related question? In a CPU with thousands of pins, how come they use N pins for ground, N pins for VCC, when it seems simpler to have continuous bar-shaped contacts? Then pins would only be necessary for signals that actually changed. I see this in computer power supplies as well, they use N separate wires to carry V+ and N more for GND, but if you need more current why not use a thicker wire and only have 2?

dmoy 3y ago
> In a CPU with thousands of pins, how come they use N pins for ground, N pins for VCC, when it seems simpler to have continuous bar-shaped contacts? I can't speak to cpus with thousands of pins, but with significantly smaller chips that often have N>1 vcc or ground, it's typically due to layout convenience. The multiple vcc may be on e.g. opposite sides of the chip, and that makes it easier to route a pure vcc signal to a spot that needs it. It's easier to route outside the chip than inside the chip, because there's more space.
- mrWiz 3y ago
  Additionally, there's also a benefit to standardization. Adding different pin styles makes the part harder to design and manufacture.
Thetawaves 3y ago
This improves the impedance of high speed signal transmission - at high speeds the currents want to flow through the ground path as close to the signal path as is possible. Said another way - designers work to reduce the total area inside the electric circuit to support high switching speeds. The additional power pins in high pin count chips serve to reduce the distance between high speed signal paths and their return ground paths. This is actually true for both ground and vcc, but is easier to visualize when working with signals and their grounds.
undersuit 3y ago
> if you need more current why not use a thicker wire and only have 2 How do you route that current in one pin to the two locations the two pins handled? You've just moved the point where the split happens from on the motherboard to on the chip package.
- gosub100 3y ago
  you could have 2 bus bars around all 4 sides of the CPU, and tap off them at the point where the die has its connectors to the "body" (enclosure?) of the package. All the die pics I've seen, the tiny gold signal wires still route around the edges (i.e. they don't join the die in the center). So a thicker bus should work for the main voltage supply. But as the sibling commenter said, it has to do with signal impedance.
  - lizknope 3y ago
    You are looking at wire bonded chips. Wire bonding is still used for chips in older process nodes and lower number of IO. This article says up to 800 IOs https://semiengineering.com/wirebond-technology-rolls-on/ https://semiengineering.com/wirebond-technology-rolls-on/ But all the high performance chips in leading edge process nodes like 3nm are flip chips. The last time I worked on a wire bond chip was in 130nm in 2004. With a wire bond chip you can only have IO for signals and power/ground around the periphery. Some wire bond chips have 2 rings of IO pads but it makes the wire bond angles complicated. It's difficult to jump over other wire bonds to get closer to the center. https://en.wikipedia.org/wiki/Flip_chip https://en.wikipedia.org/wiki/Flip_chip Flip chips have a series of bumps above the top layer of the chip. These bumps are then connected to a small PCB inside a package or some other kind of interposer. The transistors are on the bottom of the die and then up to 18 layers of metal are built on top. In a wire bond chip the heat has to go up through all that metal stackup which is usually encased in a glob top which isn't great for heat transfer. https://www.gluespec.com/blog/glob-top-encapsulation https://www.gluespec.com/blog/glob-top-encapsulation In contrast a flip chip has the die mounted upside with the top layer mounted to the PCB and the side with transistors is on top and can be directly mounted to a heat sink. Intel and AMD used to have bare die around 2000 but then mounted heat spreaders on top because sometimes people would mount the heat sink incorrectly and crack the corner of the die when tightening down non-uniformly. http://mantravlsi.blogspot.com/2014/10/flip-chip-and-wire-bonding.html http://mantravlsi.blogspot.com/2014/10/flip-chip-and-wire-bo... With a flip chip we can have over 15,000 IO in the chip. The flip chip bumps can be all over the die not just the periphery. Not only can we put IO in the center but the density of the bumps can be much higher compared to the pad points where a wire bonder would attach. As for your original question about some kind of continuous bar shaped contact we have a power grid underneath on every layer to distribute the power across the chip. This has to go from the top layer Metal18 down through vias to the transistors below Metal1. Modern chips have multiple voltages in multiple voltage domains. The DDR and PCIE sections have their own voltage requirements. The standard cells that are the combination logic within a CPU operate on much lower voltages. We have dynamic voltage control where the voltage is lowered to save power. We have voltage islands where the USB port can be shut off if nothing is plugged in or CPU core 1 is active while cores 2-4 are off saving power. This requires dedicated power / ground bumps and head switches to disconnect power to sections of the chip. I don't think we could manufacture your concept of a "bar shaped contact" because the process DRC (Design Rule Check) stuff is very rigid about what can be manufactured. Certain shapes, widths, and turns decrease the yield so they aren't allowed. https://www.vlsi-expert.com/2014/12/design-rule-check.html https://www.vlsi-expert.com/2014/12/design-rule-check.html
exmadscientist 3y ago
I've never seen it on large logic chips, but this is pretty common on power ICs. Look up TI's HotRod QFNs for a particularly well-marketed example. Of course, the fab processes here are basically stone-age (for example, 0.6um BCD is still very common), so such things are easier to do and more beneficial for high-power parts.

adhesive_wombat 3y ago

Perhaps not trivial in chip interconnects, but it's fairly abundant and a rather workable material in general (hence the bronze age). Faraday probably wouldn't have gotten very far if copper was a gas at room temperature or only occured in trace amounts and there were no other ductile, solid conductive materials on Earth.

lazide 3y ago
Sure, though carbon and salt water is also reasonably conductive. Power distribution via hydraulics instead?

undersuit 3y ago

I think they're talking about copper electrical wiring not semiconductor use. If we couldn't use simple copper to bootstrap our energy intensive aluminum industry in the 1800s we might be using rhodium.