8 ms·

Can I make a suggestion - the DE0-Nano and DE0-CV. Lots of legacy IO while being an older device family that still has a very fast and efficient compilation tim

Can I make a suggestion - the DE0-Nano and DE0-CV. Lots of legacy IO while being an older device family that still has a very fast and efficient compilation time. Hardware wise, both have vanilla SDRAM, the CV board has 7segments, PS/2 ports and VGA out. If you want to learn FPGAs, don't let tools get in the way of learning. Stick to Altera/Intel if for only 1 reason: Signaltap. SignalTap is the single best tool you can get for getting somewhere in your FPGA journey, primarily if you ever plan on interfacing with hardware or ICs outside your FPGA. That is what FPGAs are designed for, anyway. It's like superman x-ray vision for your bugs. I would recommend not using the open source tools with ice40 if only because there is no equivalent of SignalTap. Imagine having no gdb, no printf debugging, and all you have is 2 LEDs. Don't waste your time. Sure, Quartus can be annoying sometimes, but don't get distracted on tooling when you are trying to get your PS/2 keyboard or mouse interface working. Or check how many pixels your VGA horizontal back porch is, even though you think you wrote the verilog correctly. With Signaltap you cook in a highly configurable logic analyzer into the design, and you can include any IO pin, bus internal register, or state machine. It's one thing to play around in the simulator and test bench your own code, but that's rarely where the issues come up. Nothing beats actually analyzing your own design and external interfaces, warts and all, to see down to the exact clock cycle where something happened. By the way, Xilinx does have something similar as an ILA, but it's not nearly as good, and the 7 series compilation times are not gonna be as fast as the cyclone IV.

oscillonoscope 3y ago
This type of debugging is fine for people just starting out or hobbyists but won't be useful if you're trying to design HDL professionally. You really need to be able to create accurate simulations so you're not debugging on hardware the entire time. Hardware debugging takes a long time (builds can take hours) and you're more limited in terms of how many signals you can view/how many samples you can take.
- mips_r4300i 3y ago
  You are absolutely correct, and because it doesn't scale well, you have to keep it highly targeted. It all depends on what you are designing. Something DSP focused like a MJPEG encoder can be entirely simulated as it can be abstracted away from anything external. Most you would need would be a simple model of your external DRAM controller for a framebuffer. And this would definitely be both the fastest and easiest way to develop it. On the other hand, I did a job where I had to design a secure enclave accessible as a typical LBA-accessible SD card through a standard SD reader. I designed a pcb specifically to let me sniff the protocol both with a real card and my own IP. Of course, I started with implementing everything in the SD spec to the letter. It still required a crazy week of in situ debugging with dozens of card readers and cards to see why both ends violated the spec but worked anyway. In the end, I was able to design the flash translation layer fully in simulation but the SD link and phy layer were developed almost fully with the signaltap debug and compile loop.
cushychicken 3y ago
SignalTap is a delight but as the other commenter points out, it's a hard thing to deploy on most real designs due to how much space it eats.
- mwbajor 3y ago
  Xilinx has ILAs (integrated logic analyzer) which is similar. In both cases, they are just logic analyzers. You never would deploy a product with signal tap or ILAs, what would be the purpose? 1) You usually read out the ILA/Signal Tap stream using JTAG. The newer Ultrascales do have a core that allows you to not have to do this, but in most cases, JTAG is what you use. 2) For debugging, you can always load a debugging bistream with your ILA in the circuit. 3) Bottom line, ILAs take up space and are only useful for slower signals unless you want to use precious BRAMs.
dyselon 3y ago
I really like the DE0-CV in particular for having the 7 segment displays and accessible buttons and switches. When I was first getting started in FPGA stuff, I spent a lot of time just getting basic circuits to work, and you need some physical IO to get any feedback that your stuff works. It gives you a lot of things to learn on before you start worrying about VGA output or whatever (but does have a lot of interesting stuff on board for when you do want to mess around with that stuff!)

oscillonoscope 3y ago

This type of debugging is fine for people just starting out or hobbyists but won't be useful if you're trying to design HDL professionally. You really need to be able to create accurate simulations so you're not debugging on hardware the entire time. Hardware debugging takes a long time (builds can take hours) and you're more limited in terms of how many signals you can view/how many samples you can take.

mips_r4300i 3y ago
You are absolutely correct, and because it doesn't scale well, you have to keep it highly targeted. It all depends on what you are designing. Something DSP focused like a MJPEG encoder can be entirely simulated as it can be abstracted away from anything external. Most you would need would be a simple model of your external DRAM controller for a framebuffer. And this would definitely be both the fastest and easiest way to develop it. On the other hand, I did a job where I had to design a secure enclave accessible as a typical LBA-accessible SD card through a standard SD reader. I designed a pcb specifically to let me sniff the protocol both with a real card and my own IP. Of course, I started with implementing everything in the SD spec to the letter. It still required a crazy week of in situ debugging with dozens of card readers and cards to see why both ends violated the spec but worked anyway. In the end, I was able to design the flash translation layer fully in simulation but the SD link and phy layer were developed almost fully with the signaltap debug and compile loop.

cushychicken 3y ago

SignalTap is a delight but as the other commenter points out, it's a hard thing to deploy on most real designs due to how much space it eats.

mwbajor 3y ago
Xilinx has ILAs (integrated logic analyzer) which is similar. In both cases, they are just logic analyzers. You never would deploy a product with signal tap or ILAs, what would be the purpose? 1) You usually read out the ILA/Signal Tap stream using JTAG. The newer Ultrascales do have a core that allows you to not have to do this, but in most cases, JTAG is what you use. 2) For debugging, you can always load a debugging bistream with your ILA in the circuit. 3) Bottom line, ILAs take up space and are only useful for slower signals unless you want to use precious BRAMs.

dyselon 3y ago

I really like the DE0-CV in particular for having the 7 segment displays and accessible buttons and switches. When I was first getting started in FPGA stuff, I spent a lot of time just getting basic circuits to work, and you need some physical IO to get any feedback that your stuff works. It gives you a lot of things to learn on before you start worrying about VGA output or whatever (but does have a lot of interesting stuff on board for when you do want to mess around with that stuff!)