FPGAs are "programmed", or perhaps more accurately, "Synthesized" with hardware description languages like Verilog or VHDL. With typical programming, you're de

FPGAs are "programmed", or perhaps more accurately, "Synthesized" with hardware description languages like Verilog or VHDL. With typical programming, you're describing software. With VHDL / Verilog, you're describing hardware. When Verilog/VHDL "runs", its just the hardware existing, ready to react to whatever happens later. There's no code that "steps" through if-statements or loops... there's instead state-machines that get stored into memory... with their outputs being directed upon physical wires you name. As far as a "language" goes, I'd say its close to C++ Template Metaprogramming, though the syntax is very different. But the concepts are surprisingly close. C++ Templates do not compile into code, they compile into concepts and layouts... so to speak. Well, of course C++ Templates eventually turn into C++ code. But imagine if the end result were flipflops, wires, and 1-bit memory instead. Maybe I'm describing it wrong... or maybe the only way to really know is to try it yourself.