When I originally (many moons ago!) read about CXL -- I conceptualized it solely as a means to attach additional memory -- to a single CPU... Now that I read t

When I originally (many moons ago!) read about CXL -- I conceptualized it solely as a means to attach additional memory -- to a single CPU... Now that I read this article, I now also conceptualize CXL -- as a bus, that is, as a potential future PCIe bus replacement... That is, assuming that PCIe is patent-encumbered, and CXL is not -- and I don't know the current legal/patent statuses of either... Anyway, a very interesting article! There's definitely more tiers in the memory/storage (latency) hierarchy these days, and potentially room for even more... Also... >"With CXL 2.0 and CXL 3.0 which include switching, a host can access memory from one or more devices that form a pool. It’s important to note that in this kind of pooled configuration, only the resources themselves and not the contents of the memory are shared among the hosts: each region of memory can only belong to a single coherency domain. Memory sharing, which has been added to the CXL 3.0 specification, actually allows individual memory regions within pooled resources to be shared between multiple hosts." Historically, this reminds me of some of the ideas present in the the Cray-1: https://en.wikipedia.org/wiki/Cray-1 https://en.wikipedia.org/wiki/Cray-1 I'm guessing (but not knowing!) that in the future, "homebrew" supercomputers using CXL to link multiple CPUs (and GPUs/TPUs/NPUs...) to multiple nearby banks of gargantuan shared memory (HAL 9000: "I'm sorry Dave, I can't let you do that..." <g>) -- will be able to be created by people with less-than-Supercomputing-Center-budgets -- but all of that is highly speculative for the time being!