3 ms·
Also “notoriously weak” memory model even as multithreading was taking off, and > The processor may lose track of your LDx_L if you perform any memory access o
by masklinn 3y ago
Also “notoriously weak” memory model even as multithreading was taking off, and
> The processor may lose track of your LDx_L if you perform any memory access other than a matching STx_C, or if you perform a branch instruction, or if you trigger a trap (such as executing an emulated instruction), or if you execute more than 20 instructions after the LDx_L.
(LDxL and STxC are locked load and conditional store)
- colejohnson66 3y agoWhat do you mean “lose track of”?
- masklinn 3y agoDiscard / clear the lock flag, so I assume the store never succeeds (but the behaviour could be less consistent).
- pm215 3y agoThat is pretty standard for LL/SC instructions -- you'll find similar constraints on the Arm equivalent insns. In practice this doesn't matter because you only use them in a limited set of handcoded sequences to implement the atomic primitives you actually wanted, so you can always be sure that your LL/SC loop obeys the rules and makes forward progress.
- cmrdporcupine 3y agoWas going to say. x86 I think has spoiled people in terms of what they expect in terms of memory model / consistency. The answer is to be careful as a dev, and hopefully let the compiler and your libraries take care of the finer details.