I am hopeful we'll have a "miSTress" or some similar such name as followup to miST/miSTer. To adopt a cheaper, more modern, and more powerful FPGA ecosystem th

I am hopeful we'll have a "miSTress" or some similar such name as followup to miST/miSTer. To adopt a cheaper, more modern, and more powerful FPGA ecosystem that's actually supported by the yosys/nextpnr open stack. And, while at it, the control plane CPU would be standard RISC-V instead of legacy ISA (currently ARM). Something like Lattice ECP5 or GOWIN's GW2N. On that, Sipeed recently announced a cheap 135K LUT devboard[0] based on GW2N. Apparently, a version with ~500k LUT is in the works. 0. https://www.cnx-software.com/2023/10/01/sipeed-tang-mega-138k-pro-dock-features-gowin-gw5ast-fpga-risc-v-soc/ https://www.cnx-software.com/2023/10/01/sipeed-tang-mega-138...