3 ms·
> use less die area at the cost of a lower maximum clock. This makes no sense to me. Lower die area means smaller feature sizes (ie a process size change) or
by spott 3y ago
> use less die area at the cost of a lower maximum clock.
This makes no sense to me. Lower die area means smaller feature sizes (ie a process size change) or fewer transistors (ie features change). I’m not sure how you have the same features in a smaller die area and (presumably) be at the same process node and “just” sacrifice clocks.
Do you have a source for that? Or more information about how that is possible?
- sudosysgen 3y agoIt does have less L3, and maybe it's routed for longer critical paths, thereby allowing for denser packing?
- wmf 3y agoCircuit design has some interesting nuances. For example, within a given process transistors are available in different sizes: low-Vt transistors are physically larger and faster while high-Vt are smaller but slower (and there are multiple in-between sizes). Using the same design but different transistors it's possible to trade off area and clock frequency, which is exactly what AMD has done in this case. There may also be thermal considerations; a dense high-frequency design could have unacceptable hot spots so they space it out a bit to spread the heat. At a lower frequency the hot spots would be less of a problem. I can also imagine that delivering high current to a small area could cause voltage droop in the power delivery network.