3 ms·
Actual IPC increase is 1-2%. The rest is from ramping the clockspeeds. This is a problem because power consumption goes up exponentially with frequency. Go up t
by hajile 3y ago
Actual IPC increase is 1-2%. The rest is from ramping the clockspeeds. This is a problem because power consumption goes up exponentially with frequency. Go up too high and they'll be doing what AMD or Intel does where a single core is using 50+ watts to hit those peak numbers.
- svnt 3y agoPower is polynomial (it goes with the square of frequency), not exponential.
- _ph_ 3y agoHow is this a problem? It just looks that they didn't try to improve the general architecture but make one step to ramp up the clock speeds without increasing the power consumption thanks to the process step. Which is a great achievement, because any tape out on a new advanced process - here for the first time a "3nm" - is a big achievement. One has to consider that Apple now has yearly updates in its processor lineup. The next step will probably introduce more architectural changes. Only if those would stop showing up for several years in a row I would get concerned.
- hajile 3y agoWith each recent node step, you basically get +10-15% clockspeed or -30% power consumption. They just blew their entire node on a small clockspeed ramp. Now, if they want a wider core for M4, that means more transistors and more heat. They are then forced to: not go wider, decrease max clockspeed, hold max clockspeed for a pitiful amount of time, or increase power consumption. On the whole, I'd rather have a wider core and lower clockspeeds then turn the other power savings into either battery life or a few more E-cores.