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Most of the IO comes out of the FPGA fabric. This seems both very interesting but also kind of annoying. In a past life looking at these Polarfire chips, one
by bradfa 3y ago
Most of the IO comes out of the FPGA fabric. This seems both very interesting but also kind of annoying.
In a past life looking at these Polarfire chips, one downside of this kind of configuration of IO was that the bus between the FPGA fabric and the RISC-V cores was not all that fast, at least in comparison to what the FPGA fabric itself could push for IO to external devices. Not that this is likely to matter for people buying the BeagleV-Fire, but just don't let the interface speeds fool you into thinking the RISC-V cores can actually access all that IO performance without bottlenecks. Or maybe they've changed how this works since I last looked at these chips?
- snvzz 3y agoThe SERDESs seem powerful. Maybe some of them are facing or can face the RISC-V cores. My main nag with Polarfire is lack of documentation enabling support on the open stack (yosys+nextpnr). Ironically, we might end up with documentation and support obtained from reverse engineering the official tools and their databases and output. Such support is ironically very favorable to vendors that do not deserve it, e.g. iCE40 and Project iCEStorm, the first FPGA hardware supported, definitely popularized that specific FPGA architecture, which helped Lattice's sales.