3 ms·

Well thats the interesting thing. They're not really "tiny," they're just Zen 4 not optimized for crazy clockspeeds.

smoldesu 3y ago
Yeah, that's what threw me for a loop. It's not really a significant shrink on-die, though it would be interesting to see how 4c-only machines perform for their power budget. All in all a weird showing, but not entirely unexpected given how long AMD has avoided big.LITTLE for.
- brucethemoose2 3y ago
  Its not as dramatic as Intel's E cores, but its still significant enough to save a lot of space (hence AMD could make slightly bigger 16-core CCDs. with them).
- freeqaz 3y ago
  Every little bit of die shrinkage increases yield too. Defect rates during the lithography are proportional to mm^2 of die area, so these chips are likely more profitable for AMD to ship too. Gives them a way to squeeze more money out due to less wasted defective chips.
- atq2119 3y ago
  Bergamo (server chips) are 4c-only machines, so you could look at benchmarks for those. They're pretty impressive.
  - brucethemoose2 3y ago
    And the key here is they are using 16-core CCDs. The IO die is not even fully populated! I'm sure there is a technical reason they didn't make Bergamo bigger (bandwidth starvation?), but it almost feels like they are trying not to clobber Intel too hard.
    - adgjlsfhk1 3y ago
      I think the bigger part is that they are running out of bandwidth to feed the cores. They already bumped the ram up to 12 channel, and the chip is already mostly cache. They could pretty easily make a 256 core chip if they wanted, but those cores would spend all of their time waiting for data.
      - brucethemoose2 3y ago
        And if they build 3D cache capability into the Bergamo CCD, that would still blow up the die size (from the TSVs) and not alleviate some workloads anyway. For the Zen 3 generation, AMD quietly mentioned that they skipped the 5950X3D because there was too much congestion between the CCDs, thanks to all the extra L3 they were trying to access. The IF links got saturated. Maybe something similar would happen to Bergamo as well. Even if there's enough memory bandwidth, the IO die just gets saturated with all the CCD slots active.
- makomk 3y ago
  It's a pretty significant shrink given that a huge chunk of the core's die area is L2 cache which doesn't really shrink at all. If I remember rightly this was better explained in previous coverage when Zen 4c was first announced.

Yeah, that's what threw me for a loop. It's not really a significant shrink on-die, though it would be interesting to see how 4c-only machines perform for their power budget. All in all a weird showing, but not entirely unexpected given how long AMD has avoided big.LITTLE for.

brucethemoose2 3y ago
Its not as dramatic as Intel's E cores, but its still significant enough to save a lot of space (hence AMD could make slightly bigger 16-core CCDs. with them).
freeqaz 3y ago
Every little bit of die shrinkage increases yield too. Defect rates during the lithography are proportional to mm^2 of die area, so these chips are likely more profitable for AMD to ship too. Gives them a way to squeeze more money out due to less wasted defective chips.
atq2119 3y ago
Bergamo (server chips) are 4c-only machines, so you could look at benchmarks for those. They're pretty impressive.
- brucethemoose2 3y ago
  And the key here is they are using 16-core CCDs. The IO die is not even fully populated! I'm sure there is a technical reason they didn't make Bergamo bigger (bandwidth starvation?), but it almost feels like they are trying not to clobber Intel too hard.
  - adgjlsfhk1 3y ago
    I think the bigger part is that they are running out of bandwidth to feed the cores. They already bumped the ram up to 12 channel, and the chip is already mostly cache. They could pretty easily make a 256 core chip if they wanted, but those cores would spend all of their time waiting for data.
    - brucethemoose2 3y ago
      And if they build 3D cache capability into the Bergamo CCD, that would still blow up the die size (from the TSVs) and not alleviate some workloads anyway. For the Zen 3 generation, AMD quietly mentioned that they skipped the 5950X3D because there was too much congestion between the CCDs, thanks to all the extra L3 they were trying to access. The IF links got saturated. Maybe something similar would happen to Bergamo as well. Even if there's enough memory bandwidth, the IO die just gets saturated with all the CCD slots active.
makomk 3y ago
It's a pretty significant shrink given that a huge chunk of the core's die area is L2 cache which doesn't really shrink at all. If I remember rightly this was better explained in previous coverage when Zen 4c was first announced.