The Pentium architecture pops up from time to time (after the Netburst architecture Intel rolled back closer to the original Pentium architecture, and now Larra

The Pentium architecture pops up from time to time (after the Netburst architecture Intel rolled back closer to the original Pentium architecture, and now Larrabee/MIC uses the same Pentium cores). At that time it was efficient because the memory clock was not very different from the CPU clock (6x-10x ratio) - the memory access did not cost a lot of CPU cycles, so the CPU had a decent performance without a big on-die cache. At higher clocks (more than 1GHz, ratio >10x) the Pentium architecture (Pentium III at that time) showed its age and had to be replaced (with the not-so-good Netburst). Right now the CPU/memory ratio is higher (20x and more), so the CPUs require big caches to compensate. The CPU cache has a huge transistor count, being SRAM (Static RAM, very low latency). Every SRAM bit is implemented with 6 transistors, so for 1MB of cache you need ~50 million transistors.