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I don't understand "compiling code" as a metric. Do you mean Swift and Objective-C? Or do you mean general things like Rust and C++? Based on multiple benchmar
by deaddodo 3y ago
I don't understand "compiling code" as a metric. Do you mean Swift and Objective-C? Or do you mean general things like Rust and C++?
Based on multiple benchmarks, the Ryzen 6000 series and Alder Lake series should outperform the M2 Ultra pretty drastically (200-300%, which is well above the M3 general uplift of 20%) unless there's a severe disk bottleneck, which is going to be more of a SSD/PCIe issue than a CPU one (and something that can be configured/improved on PCs).
- wood_spirit 3y agoI was talking about when the first generation M1 came out and it was faster than normal contemporary desktops at developer stuff like compiling Java and c/c++ and objectiveC (was this before iOS went swift? I can’t remember). Lots of devs got one and praised it to bits on HN. And my builds were basically twice as fast. These days, due to various constraints with tooling my current company still uses, I’m on a new x86 MBP, and it feels slower and hotter and noisier. But it’s not a desktop.
- inkyoto 3y ago> Based on multiple benchmarks, the Ryzen 6000 series and Alder Lake series should outperform the M2 Ultra pretty drastically (200-300%, which is well above the M3 general uplift of 20%) unless there's a severe disk bottleneck, which is going to be more of a SSD/PCIe issue than a CPU one (and something that can be configured/improved on PCs). Compilation is strongly memory bound, especially large builds. Rust and Haskell compilers regularly clock a upward of 70 Gb/sec of the memory throughput on the parallel builds of some small to most medium size code bases. Large C++ builds should be the same. Synthetic benchmarks are a poor reflection of such workloads. Having said that, it does not matter how fast is the CPU if it stalls on the memory access, if e.g. the memory bus is not wide enough. Max's 512-bit wide memory bus at 400Gb/sec and Ultra's 1024-bit memory bus at 800Gb/sec can feed the L2 cache much faster resulting in a more even CPU core utilisation and the workload spread.