I've done some peephole optimizations at the initial machine instruction lowering phase (in LLVM) because there were some quirks of the register files in the ta

I've done some peephole optimizations at the initial machine instruction lowering phase (in LLVM) because there were some quirks of the register files in the target architecture and that was just the best place to optimize (after register allocation) - you didn't want to access two operands from the same register bank and have the result go back into the same register bank (if you could avoid it) because it would cost an extra cycle or two. So we went through and identified those cases and fixed them up (where possible).