I see that the burst length for LPDDR4/LPDDR5 is configurable as either 16 transfers (32B) or 32 transfers (64B) which means that fetching a single 128B cache l

I see that the burst length for LPDDR4/LPDDR5 is configurable as either 16 transfers (32B) or 32 transfers (64B) which means that fetching a single 128B cache line requires Apple M memory controller to issue 2 or 4 read bursts depending on the setting used. According to the page 78 from https://www.micron.com/-/media/client/global/documents/products/data-sheet/dram/mobile-dram/low-power-dram/lpddr4/z19m_embedded_lpddr4_lpddr4x.pdf https://www.micron.com/-/media/client/global/documents/produ..., burst read operation will take 16 clock cycles to clock in, and roughly 4 more cycles to get the data out. At 2133Mhz clock cycle is 468 ps or 0.46 ns so to get 64 bytes out it will take 20 cycles x 0.46 ns = 9.2 ns. This means that to populate the 128B cache line it will take at least two such bursts leading to a total latency of 18.4 ns. This latency translates to ~6GB/s of burst reads. I guess this is a number only for a single channel and it's relatively close to what Micron mentions in the PDF: "Up to 8.5 GB/s per die". What I don't understand is how the LPDDR4 data rate transfer of 3200 MT/s (~25GB/s) is achieved then? The biggest package Micron LPDDR4 module comes in is 2 channels, hence, per their numbers we get a maximum bandwidth of 2 x 8.5GB/s = 17GB/s.