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Hm, qualcomms seems to have some point there, but also seems to be driven by wanting to reuse more ARM tech. I guess google forcing RV64GC or RV64G_Zigs could

Hm, qualcomms seems to have some point there, but also seems to be driven by wanting to reuse more ARM tech. I guess google forcing RV64GC or RV64G_Zigs could be the tie braker here. But while removing or changing the C instruction when it's rolled out isn't really an option as long as it's mostly about emulator testing they probably don't care too much.

snvzz 3y ago
Nah, Qualcomm just wants to reuse Nuvia core with RISC-V frontend making minimal changes. Their proposal is no good[0]. >No clearly discernible technical benefit for native RISC-V cores, and some clear technical disadvantages for both low-end and highend implementations 0. https://lists.riscv.org/g/tech-profiles/attachment/353/0/RISCV-20231004-C.pdf https://lists.riscv.org/g/tech-profiles/attachment/353/0/RIS...
- jabl 3y ago
  Alternatively, you could say that Sifive just wants to retain their investment into cores with the C extension. Or that Krste is so wedded to the idea of "RISC purity + C + fusion" as an alternative to more complex instructions that he invents justifications for it. In reality, it seems logical to me that all the players here have an interest in the long term health of RISC-V, including applicability to higher end cores. Qualcomm is showing data supporting their position. And Sifive is showing data supporting their position. Will be interesting to see which wins, and whoever it will be it'll hopefully be the best for the long term health of RISC-V even if it means one of the parties needs to partially redesign their cores.
  - brucehoult 3y ago
    It's entirely possible to have both in the same CPU. At the same time, with a program using any mixture of C extension and Qualcomm's Znew extension that it wants to. The opcodes don't clash. This is an application profile question -- what extensions are required in the CPU in order to run shrink-wrapped software -- not an ISA or hardware question.

snvzz 3y ago

Nah, Qualcomm just wants to reuse Nuvia core with RISC-V frontend making minimal changes. Their proposal is no good[0]. >No clearly discernible technical benefit for native RISC-V cores, and some clear technical disadvantages for both low-end and highend implementations 0. https://lists.riscv.org/g/tech-profiles/attachment/353/0/RISCV-20231004-C.pdf https://lists.riscv.org/g/tech-profiles/attachment/353/0/RIS...

jabl 3y ago
Alternatively, you could say that Sifive just wants to retain their investment into cores with the C extension. Or that Krste is so wedded to the idea of "RISC purity + C + fusion" as an alternative to more complex instructions that he invents justifications for it. In reality, it seems logical to me that all the players here have an interest in the long term health of RISC-V, including applicability to higher end cores. Qualcomm is showing data supporting their position. And Sifive is showing data supporting their position. Will be interesting to see which wins, and whoever it will be it'll hopefully be the best for the long term health of RISC-V even if it means one of the parties needs to partially redesign their cores.
- brucehoult 3y ago
  It's entirely possible to have both in the same CPU. At the same time, with a program using any mixture of C extension and Qualcomm's Znew extension that it wants to. The opcodes don't clash. This is an application profile question -- what extensions are required in the CPU in order to run shrink-wrapped software -- not an ISA or hardware question.