3 ms·

Yes, in embedded roles. Western Digital's hard driver controllers, NVidia's power controllers, stuff like that and probably a lot more too. Probably more that

Yes, in embedded roles. Western Digital's hard driver controllers, NVidia's power controllers, stuff like that and probably a lot more too. Probably more that don't make the news, though this is mostly a thing for companies with the scale and silicon experience that customizing a core to their needs makes business sense.

hajile 3y ago
Even Apple has added job postings for RISC-V devs.
- klelatti 3y ago
  They have also just signed a new long term contract with Arm.
  - hajile 3y ago
    They use a couple dozen Chinook of soft cores. These are supposedly small 64-bit cores, but ARM requires features they likely don't use and ARM requires payment for each of these cores. Switching these to RISC-V could save area and money without having any effect on their big cores. SiFive claims nearly A78 performance in half the die area. In wearables, this represents a lot of savings in area and probably in power consumption too. This is another move Apple might make as ISA backward-compatibility isn't very important in that market while cost and power are.
    - klelatti 3y ago
      Sorry I take all these SiFive claims with a huge pinch of salt since they did this, comparing 7nm vs 10nm: https://twitter.com/dylan522p/status/1415395415000817664 https://twitter.com/dylan522p/status/1415395415000817664 Great way to undermine your credibility.
      - hajile 3y ago
        That's Samsung 10nm LP vs something something 7nm. Not the best comparison, but one that would still imply some amount of area advantage for stock 7nm nodes. A78 on SD845 used 64kb L1 vs 32kb L1 on P670 (a 32kb variant is available, but would get significantly worse performance relative to P670). Likewise, other things like the uop cache and 32-bit frontend add a lot to the size/power of A78 as ARM themselves bragged that their frontend got 75% smaller when they dropped the uop cache and 32-bit support in newer mid-core designs. I'd guess this frontend difference alone accounts for most of the area difference between the two.
        klelatti 3y ago
        That sounds like a very fair comparison. And to be clear I was referring to SiFive's credibility in the comment above and not yours!
    - Symmetry 3y ago
      They aren't claiming A78 performance, they're claiming A78 performance/frequency. Since there are microarchitectural tradeoffs between frequency and IPC in terms of things like how many FO4s to use in pipeline stages these claims aren't as significant as they could be. If you have a super embedded system where your clock speed is tied to your memory frequency in a way where that's the limiting factor then performance/frequency can be a useful metic, but not in any system with caches.

hajile 3y ago

Even Apple has added job postings for RISC-V devs.

klelatti 3y ago
They have also just signed a new long term contract with Arm.
- hajile 3y ago
  They use a couple dozen Chinook of soft cores. These are supposedly small 64-bit cores, but ARM requires features they likely don't use and ARM requires payment for each of these cores. Switching these to RISC-V could save area and money without having any effect on their big cores. SiFive claims nearly A78 performance in half the die area. In wearables, this represents a lot of savings in area and probably in power consumption too. This is another move Apple might make as ISA backward-compatibility isn't very important in that market while cost and power are.
  - klelatti 3y ago
    Sorry I take all these SiFive claims with a huge pinch of salt since they did this, comparing 7nm vs 10nm: https://twitter.com/dylan522p/status/1415395415000817664 https://twitter.com/dylan522p/status/1415395415000817664 Great way to undermine your credibility.
    - hajile 3y ago
      That's Samsung 10nm LP vs something something 7nm. Not the best comparison, but one that would still imply some amount of area advantage for stock 7nm nodes. A78 on SD845 used 64kb L1 vs 32kb L1 on P670 (a 32kb variant is available, but would get significantly worse performance relative to P670). Likewise, other things like the uop cache and 32-bit frontend add a lot to the size/power of A78 as ARM themselves bragged that their frontend got 75% smaller when they dropped the uop cache and 32-bit support in newer mid-core designs. I'd guess this frontend difference alone accounts for most of the area difference between the two.
      - klelatti 3y ago
        That sounds like a very fair comparison. And to be clear I was referring to SiFive's credibility in the comment above and not yours!
  - Symmetry 3y ago
    They aren't claiming A78 performance, they're claiming A78 performance/frequency. Since there are microarchitectural tradeoffs between frequency and IPC in terms of things like how many FO4s to use in pipeline stages these claims aren't as significant as they could be. If you have a super embedded system where your clock speed is tied to your memory frequency in a way where that's the limiting factor then performance/frequency can be a useful metic, but not in any system with caches.