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So little about chip success is down to just the core. Sure, some basic performance aspects, clock range, area and thus cores/chip. What about inter-core perf
by markhahn 3y ago
So little about chip success is down to just the core. Sure, some basic performance aspects, clock range, area and thus cores/chip. What about inter-core performance? Memory interface?
There's still no real synergy between CPUs and GPUs, even though they get less different with time. No one seems to have a decent plan for how to balance local memory resources with cache-coherency over CXL. Inter-system networking seems to be frozen in 1980 (just with faster serdes). Does in-chip and inter-chip optical change anything, or does it just mean littering the place with tranceivers?
- aklju90709 3y agoIs that where AMD is innovating? Getting in early (for x86) on chiplet design, pushing Heterogeneous System Architecture (HSA) etc?
- beebeepka 3y agoThey've been pushing the HSA buttons since they acquired ATi back in 2006. Are we there yet?
- markhahn 3y agohave they? I haven't noticed it in recent years. it seems like everyone settles for ugly, barely usable interfaces like CUDA, OpenCL, and then scabs them over with a higher-level interface like tensorflow.
- Salgat 3y agoIt's a real shame that AMD didn't embrace HSA for the long term, it's the future of computing. Intel's QuickSync is very popular with certain folks for streaming, and HSA would have taken that a step further.
- gigatexal 3y agoSeems this is the approach Apple has taken with the M chips. Everything is unified more or less. Myabe one day in the future the CPU will just be one fpga that recompiles itself for a given usecase and codepaths become hardware paths and then goes back to general for the next task.
- p_l 3y agoMy understanding is that later pre-Zen APUs and Zen chips all essentially have the HSA hardware side... it's just that AMD never managed to prepare a long-term coherent software offering like nvidia did with CUDA. So outside of one-offs or very closed platforms like consoles, the HSA capabilities were just... lying there, used as super fast PCI-e alternative to access the GPU. Now consider that with Phoenix Point APUs you have Zen 4 CPU, memory controllers, IO controller, RDNA3 GPU, and the XDNA "transputer-like" coprocessor, all hanging off common cache coherent transport (Infinity Fabric). All the hardware parts are there.
- markhahn 3y agoyes, I was thinking of HSA, but they don't seem to be working on it. I think it turned out to be hard, and therefore expensive, and they got distracted by staying alive by developing decent processors. I think we could argue that tensorflow and/or pytorch has displaced any HSA interest, too. These are programming interfaces that do an OK job of abstracting from the hardware details, and are totally embraced by the most demanding field (AI).
- mpercival531 3y agoThey have abandoned it at their lowest to focus on Zen. Now they seem to start picking up the slack. Upcoming Instinct MI300 APU brings HBM as unified system memory, together with hardware cache coherency between CPU cores and GPUs within and across NUMA nodes.
- CoastalCoder 3y agoFunny timing. In the wee hours of this morning, I was trying to figure out why my attempts to build LLVM 17.0.3 from source were failing because it couldn't find an HSA-related symbol. My impression was that the build-system's support for using HSA was a little wonky, but I'm not sure if that's fair. IIRC I worked around the issue by not trying to build LLVM's openmp code.
- hinkley 3y agoWe have a few programming languages today that can deal with NUMA, but we still design cpus for C. As caches have gotten bigger I’ve wondered when or if we will treat them as local memory instead of trying to maintain an illusion of cache coherency at a high cost.
- mappu 3y agoOn x86 the cache is implicit when you touch memory, and there are many ISA ops (push, call, ...) that implicitly update stack memory. But if you never call those, it is possible to access the cache explicitly. Coreboot have a custom in-tree compiler, ROMCC [1] that compiles C to a subset of x86 that never emits memory operations. They use this to treat cache as RAM [2] for a brief period during early boot before the RAM itself gets initialized. 1. https://github.com/wt/coreboot/tree/master/util/romcc https://github.com/wt/coreboot/tree/master/util/romcc The whole compiler is a single C file 2. https://www.coreboot.org/data/yhlu/cache_as_ram_lb_09142006.pdf https://www.coreboot.org/data/yhlu/cache_as_ram_lb_09142006.... Perform s/LinuxBIOS/Coreboot/ in your head as you read
- automatic6131 3y ago>No one seems to have a decent plan for how to balance local memory resources with cache-coherency over CXL I have seen a patent application for a technology from {big hardware company} addressing exactly this. Dunno if the approach will work, but there are definitely plans