Could use some TDP figures for SoCs this core appears in. And benchmarks on those (other than synthetic benchmarks to show L1/L2 cache behaviour etc). Design l

Could use some TDP figures for SoCs this core appears in. And benchmarks on those (other than synthetic benchmarks to show L1/L2 cache behaviour etc). Design looks good & beefy. But implementation is the other part of the equation. Or thermal throttling depending on device it's in.