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How soon do people think that we'll get in-memory computing chips?

by aperrien 3y ago

charcircuit 3y ago
Never in practical designs due to thermal issues
- dvh 3y ago
  If we create 1-dimensional memory we could radiate heat to 2 dimensions.
nvgeele 3y ago
No idea, but it's being worked on: https://www.planetanalog.com/dram-for-energy-and-area-efficient-analog-in-memory-computing/ https://www.planetanalog.com/dram-for-energy-and-area-effici... (via https://www.imec-int.com/en/articles/igzo-based-dram-energy-and-area-efficient-analog-memory-computing https://www.imec-int.com/en/articles/igzo-based-dram-energy-...)
moring 3y ago
Computing in the actual storage banks seems a bit over-the-top to me, but I always wondered about computing in the "currently open row". It seems like an obvious optimization candidate for fast memset() and memcpy(), by setting that row from another source than the storage bank, selectively loading or storing it, and shifting its contents around.
- namibj 3y ago
  Two recent (weeks) papers/presentations on: doing just that (LUT at the row buffer) https://youtu.be/9t1FJQ6nNw4 https://youtu.be/9t1FJQ6nNw4; doing parallel sense in NAND for computing AND between rows (which they call pages, but in DRAM they're called rows. It's the same concept, though.) https://youtu.be/QWL2Rw_VhHg https://youtu.be/QWL2Rw_VhHg
bjourne 3y ago
As soon as memristors become viable for general-purpose computing.
RetroTechie 3y ago
I've always thought it logical to integrate RAM & cpu. Look over the course of history: there's often a roughly-fixed ratio between cpu performance & RAM bandwidth (+ size), and cpu/memory <-> graphics interconnect speed. Any of those factors get too far out of wack, and you've got a machine with poor bang/$. GPU integration is old now. Ok I've read there's a mismatch between silicon processes used for logic (like cpu/gpu etc) and memory? But hey, this is 2023. Chiplets? Stacked dies? Or just do the best with available tech? It's not like there are no ICs that integrate RAM & compute. With the right architecture, the "memory wall" could be (mostly) a thing of the past. With enough cores & on-chip RAM bandwidth, maybe specialized gpu processing wouldn't even be needed anymore? For example: https://en.wikipedia.org/wiki/Massively_parallel_processor_array https://en.wikipedia.org/wiki/Massively_parallel_processor_a...
reportingsjr 3y ago
Who knows? IBM Research just released info on their updated compute in memory chip [0]. Intriguing, but it doesn't provide a ton of insight in to whether or not it will be commercially viable any time soon. 0: https://research.ibm.com/blog/northpole-ibm-ai-chip https://research.ibm.com/blog/northpole-ibm-ai-chip

How soon do people think that we'll get in-memory computing chips?

charcircuit 3y ago

Never in practical designs due to thermal issues

dvh 3y ago
If we create 1-dimensional memory we could radiate heat to 2 dimensions.

nvgeele 3y ago

No idea, but it's being worked on: https://www.planetanalog.com/dram-for-energy-and-area-efficient-analog-in-memory-computing/ https://www.planetanalog.com/dram-for-energy-and-area-effici... (via https://www.imec-int.com/en/articles/igzo-based-dram-energy-and-area-efficient-analog-memory-computing https://www.imec-int.com/en/articles/igzo-based-dram-energy-...)

moring 3y ago

Computing in the actual storage banks seems a bit over-the-top to me, but I always wondered about computing in the "currently open row". It seems like an obvious optimization candidate for fast memset() and memcpy(), by setting that row from another source than the storage bank, selectively loading or storing it, and shifting its contents around.

namibj 3y ago
Two recent (weeks) papers/presentations on: doing just that (LUT at the row buffer) https://youtu.be/9t1FJQ6nNw4 https://youtu.be/9t1FJQ6nNw4; doing parallel sense in NAND for computing AND between rows (which they call pages, but in DRAM they're called rows. It's the same concept, though.) https://youtu.be/QWL2Rw_VhHg https://youtu.be/QWL2Rw_VhHg

bjourne 3y ago

As soon as memristors become viable for general-purpose computing.

RetroTechie 3y ago

I've always thought it logical to integrate RAM & cpu. Look over the course of history: there's often a roughly-fixed ratio between cpu performance & RAM bandwidth (+ size), and cpu/memory <-> graphics interconnect speed. Any of those factors get too far out of wack, and you've got a machine with poor bang/$. GPU integration is old now. Ok I've read there's a mismatch between silicon processes used for logic (like cpu/gpu etc) and memory? But hey, this is 2023. Chiplets? Stacked dies? Or just do the best with available tech? It's not like there are no ICs that integrate RAM & compute. With the right architecture, the "memory wall" could be (mostly) a thing of the past. With enough cores & on-chip RAM bandwidth, maybe specialized gpu processing wouldn't even be needed anymore? For example: https://en.wikipedia.org/wiki/Massively_parallel_processor_array https://en.wikipedia.org/wiki/Massively_parallel_processor_a...

reportingsjr 3y ago

Who knows? IBM Research just released info on their updated compute in memory chip [0]. Intriguing, but it doesn't provide a ton of insight in to whether or not it will be commercially viable any time soon. 0: https://research.ibm.com/blog/northpole-ibm-ai-chip https://research.ibm.com/blog/northpole-ibm-ai-chip