It's common to have high performance CPU cores for the main tasks yet still have small microcontroller cores sprinkled all over the place for specific sub-block

It's common to have high performance CPU cores for the main tasks yet still have small microcontroller cores sprinkled all over the place for specific sub-block management, even in FPGAs. For example, a small 5-stage pipelined VexRiscv CPU take around 2000 logic elements. That's nothing in today's large FPGAs. Add, say, 4KB of RAM and put it right next to the complex HW core that you want to manage and you have the equivalent of a complex FSM that's programmable without any worries about having to share cycles with other processes and missing out events with hard real-time requirements. It's done all the time, and it's great.